Skip to content

Commit

Permalink
HW: Update upstream mor1kx
Browse files Browse the repository at this point in the history
  • Loading branch information
@wallento
wallento committed Apr 9, 2017
1 parent 393448a commit 3d31090
Show file tree
Hide file tree
Showing 23 changed files with 757 additions and 321 deletions.
76 changes: 42 additions & 34 deletions src/soc/hw/mor1kx/cappuccino.core
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,40 +8,48 @@ name = openrisc:mor1kx:cappuccino
file_type = verilogSource
usage = sim synth
files =
verilog/mor1kx_branch_prediction.v
verilog/mor1kx_bus_if_wb32.v
verilog/mor1kx_cfgrs.v
verilog/mor1kx_cpu_cappuccino.v
verilog/mor1kx_cpu.v
verilog/mor1kx_ctrl_cappuccino.v
verilog/mor1kx_dcache.v
verilog/mor1kx_decode_execute_cappuccino.v
verilog/mor1kx_decode.v
verilog/mor1kx_dmmu.v
verilog/mor1kx_execute_alu.v
verilog/mor1kx_execute_ctrl_cappuccino.v
verilog/mor1kx_fetch_cappuccino.v
verilog/mor1kx_icache.v
verilog/mor1kx_immu.v
verilog/mor1kx_lsu_cappuccino.v
verilog/mor1kx_pic.v
verilog/mor1kx_rf_cappuccino.v
verilog/mor1kx_simple_dpram_sclk.v
verilog/mor1kx_store_buffer.v
verilog/mor1kx_ticktimer.v
verilog/mor1kx_true_dpram_sclk.v
verilog/mor1kx.v
verilog/mor1kx_wb_mux_cappuccino.v
verilog/mor1kx_cache_lru.v

[fileset include_files]
file_type = verilogSource
is_include_file = true
usage = sim synth
files =
verilog/mor1kx-defines.v
verilog/mor1kx-sprs.v
verilog/mor1kx_utils.vh
verilog/mor1kx-defines.v[is_include_file]
verilog/mor1kx-sprs.v[is_include_file]
verilog/mor1kx_utils.vh[is_include_file]
verilog/mor1kx_branch_predictor_gshare.v
verilog/mor1kx_branch_predictor_simple.v
verilog/mor1kx_branch_predictor_saturation_counter.v
verilog/mor1kx_branch_prediction.v
verilog/mor1kx_bus_if_wb32.v
verilog/mor1kx_cache_lru.v
verilog/mor1kx_cfgrs.v
verilog/mor1kx_cpu_cappuccino.v
verilog/mor1kx_cpu_espresso.v
verilog/mor1kx_cpu_prontoespresso.v
verilog/mor1kx_cpu.v
verilog/mor1kx_ctrl_cappuccino.v
verilog/mor1kx_ctrl_espresso.v
verilog/mor1kx_ctrl_prontoespresso.v
verilog/mor1kx_dcache.v
verilog/mor1kx_decode_execute_cappuccino.v
verilog/mor1kx_decode.v
verilog/mor1kx_dmmu.v
verilog/mor1kx_execute_alu.v
verilog/mor1kx_execute_ctrl_cappuccino.v
verilog/mor1kx_fetch_cappuccino.v
verilog/mor1kx_fetch_espresso.v
verilog/mor1kx_fetch_prontoespresso.v
verilog/mor1kx_fetch_tcm_prontoespresso.v
verilog/mor1kx_icache.v
verilog/mor1kx_immu.v
verilog/mor1kx_lsu_cappuccino.v
verilog/mor1kx_lsu_espresso.v
verilog/mor1kx_pcu.v
verilog/mor1kx_pic.v
verilog/mor1kx_rf_cappuccino.v
verilog/mor1kx_rf_espresso.v
verilog/mor1kx_simple_dpram_sclk.v
verilog/mor1kx_store_buffer.v
verilog/mor1kx_ticktimer.v
verilog/mor1kx_true_dpram_sclk.v
verilog/mor1kx.v
verilog/mor1kx_wb_mux_cappuccino.v
verilog/mor1kx_wb_mux_espresso.v

# XXX: include params and other stuff from upstream?
# https://github.com/openrisc/orpsoc-cores/blob/master/cores/mor1kx/mor1kx.core
2 changes: 1 addition & 1 deletion src/soc/hw/mor1kx/verilog/mor1kx-defines.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -258,7 +258,7 @@
// mor1kx breaks up the VR2 version register to be 3 8-bit fields
// MSB is major version, middle byte is minor version number
// and final byte is the pipeline identifier.
`define MOR1KX_VERSION_MAJOR 8'd4
`define MOR1KX_VERSION_MAJOR 8'd5
`define MOR1KX_VERSION_MINOR 8'd0

// mor1kx implementation-specific register definitions
Expand Down
40 changes: 36 additions & 4 deletions src/soc/hw/mor1kx/verilog/mor1kx-sprs.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,21 @@

`define OR1K_SPR_PC_BASE {5'd7}
`define OR1K_SPR_PCCR0_ADDR {5'd7,11'd0}
`define OR1K_SPR_PCCR1_ADDR {5'd7,11'd1}
`define OR1K_SPR_PCCR2_ADDR {5'd7,11'd2}
`define OR1K_SPR_PCCR3_ADDR {5'd7,11'd3}
`define OR1K_SPR_PCCR4_ADDR {5'd7,11'd4}
`define OR1K_SPR_PCCR5_ADDR {5'd7,11'd5}
`define OR1K_SPR_PCCR6_ADDR {5'd7,11'd6}
`define OR1K_SPR_PCCR7_ADDR {5'd7,11'd7}
`define OR1K_SPR_PCMR0_ADDR {5'd7,11'd8}
`define OR1K_SPR_PCMR1_ADDR {5'd7,11'd9}
`define OR1K_SPR_PCMR2_ADDR {5'd7,11'd10}
`define OR1K_SPR_PCMR3_ADDR {5'd7,11'd11}
`define OR1K_SPR_PCMR4_ADDR {5'd7,11'd12}
`define OR1K_SPR_PCMR5_ADDR {5'd7,11'd13}
`define OR1K_SPR_PCMR6_ADDR {5'd7,11'd14}
`define OR1K_SPR_PCMR7_ADDR {5'd7,11'd15}

`define OR1K_SPR_PM_BASE {5'd8}
`define OR1K_SPR_PMR_ADDR {5'd8,11'd0}
Expand Down Expand Up @@ -319,7 +333,7 @@
// FPCSR flags
`define OR1K_FPCSR_ALLF `OR1K_FPCSR_DZF:`OR1K_FPCSR_OVF
// FPCSR reset value
`define OR1K_FPCSR_RESET_VALUE `OR1K_FPCSR_WIDTH'd1
`define OR1K_FPCSR_RESET_VALUE `OR1K_FPCSR_WIDTH'd0
// FPCSR extention: maskable FPU flags.
// -vvvv- uncomment the next line to switch the extention on -vvvv-
//`define OR1K_FPCSR_MASK_FLAGS
Expand All @@ -335,9 +349,27 @@
`define OR1K_FPCSR_MASK_DZF 20
// bus select
`define OR1K_FPCSR_MASK_ALL `OR1K_FPCSR_MASK_DZF:`OR1K_FPCSR_MASK_OVF
// reset value. enables: dzf,inf,ivf,snf,ovf
`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'b1_1100_0101

// reset value.
`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'd0

// PCU PCMR bits
`define OR1K_PCMR_CP 0
`define OR1K_PCMR_RSVD_1 1
`define OR1K_PCMR_CISM 2
`define OR1K_PCMR_CIUM 3
`define OR1K_PCMR_LA 4
`define OR1K_PCMR_SA 5
`define OR1K_PCMR_IF 6
`define OR1K_PCMR_DCM 7
`define OR1K_PCMR_ICM 8
`define OR1K_PCMR_IFS 9
`define OR1K_PCMR_LSUS 10
`define OR1K_PCMR_BS 11
`define OR1K_PCMR_DTLBM 12
`define OR1K_PCMR_ITLBM 13
`define OR1K_PCMR_DDS 14
`define OR1K_PCMR_WPE 25:15
`define OR1K_PCMR_RSVD_2 31:26

// Implementation-specific SPR defines
`define MOR1KX_SPR_SR_WIDTH 16
Expand Down
126 changes: 4 additions & 122 deletions src/soc/hw/mor1kx/verilog/mor1kx.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@ module mor1kx
parameter FEATURE_TIMER = "ENABLED",
parameter FEATURE_DEBUGUNIT = "NONE",
parameter FEATURE_PERFCOUNTERS = "NONE",
parameter OPTION_PERFCOUNTERS_NUM = 0,
parameter FEATURE_MAC = "NONE",

parameter FEATURE_SYSCALL = "ENABLED",
Expand Down Expand Up @@ -133,25 +134,6 @@ module mor1kx
input [31:0] dwbm_dat_i,
input dwbm_rty_i,

// Avalon interface
output [31:0] avm_d_address_o,
output [3:0] avm_d_byteenable_o,
output avm_d_read_o,
input [31:0] avm_d_readdata_i,
output [3:0] avm_d_burstcount_o,
output avm_d_write_o,
output [31:0] avm_d_writedata_o,
input avm_d_waitrequest_i,
input avm_d_readdatavalid_i,

output [31:0] avm_i_address_o,
output [3:0] avm_i_byteenable_o,
output avm_i_read_o,
input [31:0] avm_i_readdata_i,
output [3:0] avm_i_burstcount_o,
input avm_i_waitrequest_i,
input avm_i_readdatavalid_i,

input [31:0] irq_i,

// Debug interface
Expand All @@ -162,8 +144,8 @@ module mor1kx
output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
output du_ack_o,
// Stall control from debug interface
input du_stall_i,
output du_stall_o,
input du_stall_i,
output du_stall_o,

output traceport_exec_valid_o,
output [31:0] traceport_exec_pc_o,
Expand All @@ -187,8 +169,6 @@ module mor1kx

/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire avm_i_write_o; // From ibus_bridge of mor1kx_bus_if_avalon.v
wire avm_i_writedata_o; // From ibus_bridge of mor1kx_bus_if_avalon.v
wire [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o; // From mor1kx_cpu of mor1kx_cpu.v
wire [3:0] dbus_bsel_o; // From mor1kx_cpu of mor1kx_cpu.v
wire dbus_burst_o; // From mor1kx_cpu of mor1kx_cpu.v
Expand Down Expand Up @@ -334,105 +314,6 @@ module mor1kx
.wbm_dat_i (dwbm_dat_i), // Templated
.wbm_rty_i (dwbm_rty_i)); // Templated

end else if (BUS_IF_TYPE=="AVALON") begin // block: bus_gen
/* mor1kx_bus_if_avalon AUTO_TEMPLATE (
.cpu_err_o (ibus_err_i),
.cpu_ack_o (ibus_ack_i),
.cpu_dat_o (ibus_dat_i),
.avm_address_o (avm_i_address_o),
.avm_byteenable_o (avm_i_byteenable_o),
.avm_read_o (avm_i_read_o),
.avm_burstcount_o (avm_i_burstcount_o),
.avm_write_o (avm_i_write_o),
.avm_writedata_o (avm_i_writedata_o),
// Inputs
.cpu_adr_i (ibus_adr_o),
.cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}),
.cpu_req_i (ibus_req_o),
.cpu_we_i (1'b0),
.cpu_bsel_i (4'b1111),
.cpu_burst_i (ibus_burst_o),
.avm_readdata_i (avm_i_readdata_i),
.avm_waitrequest_i (avm_i_waitrequest_i),
.avm_readdatavalid_i (avm_i_readdatavalid_i),
); */

mor1kx_bus_if_avalon
#(.OPTION_AVALON_BURST_LENGTH((1<<OPTION_ICACHE_BLOCK_WIDTH)/4))
ibus_bridge
(/*AUTOINST*/
// Outputs
.cpu_err_o (ibus_err_i), // Templated
.cpu_ack_o (ibus_ack_i), // Templated
.cpu_dat_o (ibus_dat_i), // Templated
.avm_address_o (avm_i_address_o), // Templated
.avm_byteenable_o (avm_i_byteenable_o), // Templated
.avm_read_o (avm_i_read_o), // Templated
.avm_burstcount_o (avm_i_burstcount_o), // Templated
.avm_write_o (avm_i_write_o), // Templated
.avm_writedata_o (avm_i_writedata_o), // Templated
// Inputs
.clk (clk),
.rst (rst),
.cpu_adr_i (ibus_adr_o), // Templated
.cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}), // Templated
.cpu_req_i (ibus_req_o), // Templated
.cpu_bsel_i (4'b1111), // Templated
.cpu_we_i (1'b0), // Templated
.cpu_burst_i (ibus_burst_o), // Templated
.avm_readdata_i (avm_i_readdata_i), // Templated
.avm_waitrequest_i (avm_i_waitrequest_i), // Templated
.avm_readdatavalid_i (avm_i_readdatavalid_i)); // Templated

/* mor1kx_bus_if_avalon AUTO_TEMPLATE (
.cpu_err_o (dbus_err_i),
.cpu_ack_o (dbus_ack_i),
.cpu_dat_o (dbus_dat_i),
.avm_address_o (avm_d_address_o),
.avm_byteenable_o (avm_d_byteenable_o),
.avm_read_o (avm_d_read_o),
.avm_burstcount_o (avm_d_burstcount_o),
.avm_write_o (avm_d_write_o),
.avm_writedata_o (avm_d_writedata_o),
// Inputs
.cpu_adr_i (dbus_adr_o),
.cpu_dat_i (dbus_dat_o),
.cpu_req_i (dbus_req_o),
.cpu_we_i (dbus_we_o),
.cpu_bsel_i (dbus_bsel_o),
.cpu_burst_i (dbus_burst_o),
.avm_readdata_i (avm_d_readdata_i),
.avm_waitrequest_i (avm_d_waitrequest_i),
.avm_readdatavalid_i (avm_d_readdatavalid_i),
); */

mor1kx_bus_if_avalon
#(.OPTION_AVALON_BURST_LENGTH((1<<OPTION_DCACHE_BLOCK_WIDTH)/4))
dbus_bridge
(/*AUTOINST*/
// Outputs
.cpu_err_o (dbus_err_i), // Templated
.cpu_ack_o (dbus_ack_i), // Templated
.cpu_dat_o (dbus_dat_i), // Templated
.avm_address_o (avm_d_address_o), // Templated
.avm_byteenable_o (avm_d_byteenable_o), // Templated
.avm_read_o (avm_d_read_o), // Templated
.avm_burstcount_o (avm_d_burstcount_o), // Templated
.avm_write_o (avm_d_write_o), // Templated
.avm_writedata_o (avm_d_writedata_o), // Templated
// Inputs
.clk (clk),
.rst (rst),
.cpu_adr_i (dbus_adr_o), // Templated
.cpu_dat_i (dbus_dat_o), // Templated
.cpu_req_i (dbus_req_o), // Templated
.cpu_bsel_i (dbus_bsel_o), // Templated
.cpu_we_i (dbus_we_o), // Templated
.cpu_burst_i (dbus_burst_o), // Templated
.avm_readdata_i (avm_d_readdata_i), // Templated
.avm_waitrequest_i (avm_d_waitrequest_i), // Templated
.avm_readdatavalid_i (avm_d_readdatavalid_i)); // Templated

end else begin
initial begin
$display("Error: BUS_IF_TYPE not correct");
Expand Down Expand Up @@ -483,6 +364,7 @@ module mor1kx
.FEATURE_TIMER(FEATURE_TIMER),
.FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT),
.FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS),
.OPTION_PERFCOUNTERS_NUM(OPTION_PERFCOUNTERS_NUM),
.FEATURE_MAC(FEATURE_MAC),
.FEATURE_SYSCALL(FEATURE_SYSCALL),
.FEATURE_TRAP(FEATURE_TRAP),
Expand Down

0 comments on commit 3d31090

Please sign in to comment.