Merge pull request #46 from optimsoc/rework_na

First batch of NA rework
optimsoc · Apr 11, 2017 · 6cacc93 · 6cacc93
2 parents 9ef4100 + d6353d5
commit 6cacc93
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Showing 37 changed files with 1,950 additions and 572 deletions.
diff --git a/examples/fpga/nexys4ddr/compute_tile/rtl/verilog/compute_tile_dm_nexys4.sv b/examples/fpga/nexys4ddr/compute_tile/rtl/verilog/compute_tile_dm_nexys4.sv
@@ -76,13 +76,16 @@ module compute_tile_dm_nexys4
                       GMEM_TILE: 'x,
                       NOC_DATA_WIDTH: 32,
                       NOC_TYPE_WIDTH: 2,
-                      NOC_VCHANNELS: 3,
-                      NOC_VC_MPSIMPLE: 0,
-                      NOC_VC_DMA_REQ: 1,
-                      NOC_VC_DMA_RESP: 2,
-                      MEMORY_ACCESS: DISTRIBUTED,
                       LMEM_SIZE: LMEM_SIZE,
                       LMEM_STYLE: EXTERNAL,
+                      ENABLE_BOOTROM: 0,
+                      BOOTROM_SIZE: 0,
+                      ENABLE_DM: 1,
+                      DM_BASE: 32'h0,
+                      DM_SIZE: LMEM_SIZE,
+                      ENABLE_PGAS: 0,
+                      PGAS_BASE: 0,
+                      PGAS_SIZE: 0,
                       NA_ENABLE_MPSIMPLE: 1,
                       NA_ENABLE_DMA: 1,
                       NA_DMA_GENIRQ: 1,

diff --git a/examples/fpga/nexys4ddr/system_2x2_cccc/rtl/verilog/system_2x2_cccc_nexys4.sv b/examples/fpga/nexys4ddr/system_2x2_cccc/rtl/verilog/system_2x2_cccc_nexys4.sv
@@ -77,13 +77,16 @@ module system_2x2_cccc_nexys4
                       GMEM_TILE: 'x,
                       NOC_DATA_WIDTH: 32,
                       NOC_TYPE_WIDTH: 2,
-                      NOC_VCHANNELS: 3,
-                      NOC_VC_MPSIMPLE: 0,
-                      NOC_VC_DMA_REQ: 1,
-                      NOC_VC_DMA_RESP: 2,
-                      MEMORY_ACCESS: DISTRIBUTED,
                       LMEM_SIZE: LMEM_SIZE,
                       LMEM_STYLE: EXTERNAL,
+                      ENABLE_BOOTROM: 0,
+                      BOOTROM_SIZE: 0,
+                      ENABLE_DM: 1,
+                      DM_BASE: 32'h0,
+                      DM_SIZE: LMEM_SIZE,
+                      ENABLE_PGAS: 0,
+                      PGAS_BASE: 0,
+                      PGAS_SIZE: 0,
                       NA_ENABLE_MPSIMPLE: 1,
                       NA_ENABLE_DMA: 1,
                       NA_DMA_GENIRQ: 1,

diff --git a/examples/fpga/vcu108/compute_tile/rtl/verilog/compute_tile_dm_vcu108.sv b/examples/fpga/vcu108/compute_tile/rtl/verilog/compute_tile_dm_vcu108.sv
@@ -78,13 +78,16 @@ module compute_tile_dm_vcu108
                       GMEM_TILE: 'x,
                       NOC_DATA_WIDTH: 32,
                       NOC_TYPE_WIDTH: 2,
-                      NOC_VCHANNELS: 3,
-                      NOC_VC_MPSIMPLE: 0,
-                      NOC_VC_DMA_REQ: 1,
-                      NOC_VC_DMA_RESP: 2,
-                      MEMORY_ACCESS: DISTRIBUTED,
                       LMEM_SIZE: LMEM_SIZE,
                       LMEM_STYLE: EXTERNAL,
+                      ENABLE_BOOTROM: 0,
+                      BOOTROM_SIZE: 0,
+                      ENABLE_DM: 1,
+                      DM_BASE: 32'h0,
+                      DM_SIZE: LMEM_SIZE,
+                      ENABLE_PGAS: 0,
+                      PGAS_BASE: 0,
+                      PGAS_SIZE: 0,
                       NA_ENABLE_MPSIMPLE: 1,
                       NA_ENABLE_DMA: 1,
                       NA_DMA_GENIRQ: 1,

diff --git a/examples/fpga/vcu108/system_2x2_cccc/rtl/verilog/system_2x2_cccc_vcu108.sv b/examples/fpga/vcu108/system_2x2_cccc/rtl/verilog/system_2x2_cccc_vcu108.sv
@@ -97,13 +97,16 @@ module system_2x2_cccc_vcu108
          GMEM_TILE: 'x,
          NOC_DATA_WIDTH: 32,
          NOC_TYPE_WIDTH: 2,
-         NOC_VCHANNELS: 3,
-         NOC_VC_MPSIMPLE: 0,
-         NOC_VC_DMA_REQ: 1,
-         NOC_VC_DMA_RESP: 2,
-         MEMORY_ACCESS: DISTRIBUTED,
          LMEM_SIZE: LMEM_SIZE,
          LMEM_STYLE: EXTERNAL,
+         ENABLE_BOOTROM: 0,
+         BOOTROM_SIZE: 0,
+         ENABLE_DM: 1,
+         DM_BASE: 32'h0,
+         DM_SIZE: LMEM_SIZE,
+         ENABLE_PGAS: 0,
+         PGAS_BASE: 0,
+         PGAS_SIZE: 0,
          NA_ENABLE_MPSIMPLE: 1,
          NA_ENABLE_DMA: 1,
          NA_DMA_GENIRQ: 1,

diff --git a/examples/sim/compute_tile/tb_compute_tile.sv b/examples/sim/compute_tile/tb_compute_tile.sv
@@ -61,13 +61,16 @@ module tb_compute_tile(
                       GMEM_TILE: 0,
                       NOC_DATA_WIDTH: 32,
                       NOC_TYPE_WIDTH: 2,
-                      NOC_VCHANNELS: 3,
-                      NOC_VC_MPSIMPLE: 0,
-                      NOC_VC_DMA_REQ: 1,
-                      NOC_VC_DMA_RESP: 2,
-                      MEMORY_ACCESS: DISTRIBUTED,
                       LMEM_SIZE: LMEM_SIZE,
                       LMEM_STYLE: PLAIN,
+                      ENABLE_BOOTROM: 0,
+                      BOOTROM_SIZE: 0,
+                      ENABLE_DM: 1,
+                      DM_BASE: 32'h0,
+                      DM_SIZE: LMEM_SIZE,
+                      ENABLE_PGAS: 0,
+                      PGAS_BASE: 0,
+                      PGAS_SIZE: 0,
                       NA_ENABLE_MPSIMPLE: 1,
                       NA_ENABLE_DMA: 1,
                       NA_DMA_GENIRQ: 1,

diff --git a/examples/sim/system_2x2_cccc/tb_system_2x2_cccc.sv b/examples/sim/system_2x2_cccc/tb_system_2x2_cccc.sv
@@ -63,13 +63,16 @@ module tb_system_2x2_cccc(
                       GMEM_TILE: 'x,
                       NOC_DATA_WIDTH: 32,
                       NOC_TYPE_WIDTH: 2,
-                      NOC_VCHANNELS: 3,
-                      NOC_VC_MPSIMPLE: 0,
-                      NOC_VC_DMA_REQ: 1,
-                      NOC_VC_DMA_RESP: 2,
-                      MEMORY_ACCESS: DISTRIBUTED,
                       LMEM_SIZE: LMEM_SIZE,
                       LMEM_STYLE: PLAIN,
+                      ENABLE_BOOTROM: 0,
+                      BOOTROM_SIZE: 0,
+                      ENABLE_DM: 1,
+                      DM_BASE: 32'h0,
+                      DM_SIZE: LMEM_SIZE,
+                      ENABLE_PGAS: 0,
+                      PGAS_BASE: 0,
+                      PGAS_SIZE: 0,
                       NA_ENABLE_MPSIMPLE: 1,
                       NA_ENABLE_DMA: 1,
                       NA_DMA_GENIRQ: 1,

diff --git a/external/lisnoc/dma.core b/external/lisnoc/dma.core
@@ -15,6 +15,7 @@ files =
   rtl/dma/lisnoc_dma_initiator_nocresp.sv
   rtl/dma/lisnoc_dma_request_table.sv
   rtl/dma/lisnoc_dma_wbinterface.v
+  rtl/infrastructure/lisnoc_packet_buffer.sv
 
 [fileset include_files]
 file_type = verilogSource

diff --git a/external/lisnoc/rtl/router/lisnoc_router_arbiter.sv b/external/lisnoc/rtl/router/lisnoc_router_arbiter.sv
@@ -121,7 +121,7 @@ module lisnoc_router_arbiter (/*AUTOARG*/
          if (request_i[activeportnum] && ready_i) begin
             read_o[activeportnum] = 1'b1;
             valid_o = 1'b1;
-            if (flit_type == `FLIT_TYPE_LAST)
+            if (flit_type[1])
                nxt_activeroute = 1'b0;
          end else begin
             valid_o = 1'b0;
@@ -131,7 +131,7 @@ module lisnoc_router_arbiter (/*AUTOARG*/
          valid_o = 1'b0;
          if (|request_i & ready_i) begin
             valid_o = 1'b1;
-            nxt_activeroute = (flit_type != `FLIT_TYPE_SINGLE);
+            nxt_activeroute = !flit_type[1];
             read_o[portnum] = 1'b1;
          end
       end

diff --git a/external/lisnoc/rtl/router/lisnoc_router_input_route.v b/external/lisnoc/rtl/router/lisnoc_router_input_route.v
@@ -107,8 +107,8 @@ module lisnoc_router_input_route (/*AUTOARG*/
    // Generating the current destination selection
    assign nxt_cur_select = ( // If there is no transfer we are waiting for or the active is finished ..
                              (~active || (active && read)) &&
-                             // .. and this is valid and  the first flit in a packet ..
-                             (fifo_valid && (flit_type==`FLIT_TYPE_HEADER || flit_type==`FLIT_TYPE_SINGLE))
+                             // .. and this is valid..
+                             (fifo_valid)
                              // .. take selection from the lookup vector
                              ) ? lookup_vector[flit_dest] :
                            // take current value otherwise