sipeed/m1s-dock: fixup after rebase, switch to bl-pac

Signed-off-by: Daniel Maslowski <info@orangecms.org>
oreboot · May 21, 2023 · ded1801 · ded1801
1 parent c4bdf3e
commit ded1801
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Showing 5 changed files with 19 additions and 14 deletions.
diff --git a/src/mainboard/sipeed/m1s-dock/c906/Cargo.toml b/src/mainboard/sipeed/m1s-dock/c906/Cargo.toml
@@ -9,7 +9,12 @@ authors = [
 edition = "2021"
 
 [dependencies]
-embedded-hal = "1.0.0-alpha.8"
+bl808-pac = { git = "https://github.com/bouffalolab/bl-pac", commit = "eb62bbb", features = ["rt", "critical-section"] }
+critical-section = "1.0"
+embedded-hal = "=1.0.0-alpha.9"
+embedded-hal-nb = "=1.0.0-alpha.1"
+log = { path = "../../../../lib/log" }
 nb = "1"
-riscv = "0.9.0"
+riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }
+riscv-rt = "0.11.0"
 spin = "0.9"
diff --git a/src/mainboard/sipeed/m1s-dock/e907/Cargo.toml b/src/mainboard/sipeed/m1s-dock/e907/Cargo.toml
@@ -9,9 +9,10 @@ authors = [
 edition = "2021"
 
 [dependencies]
-bl808-pac = { git = "https://github.com/bouffalolab/bl808-pac", commit = "3bbd010", features = ["rt", "critical-section"] }
+bl808-pac = { git = "https://github.com/bouffalolab/bl-pac", commit = "eb62bbb", features = ["rt", "critical-section"] }
 critical-section = "1.0"
-embedded-hal = "=1.0.0-alpha.8"
+embedded-hal = "=1.0.0-alpha.9"
+embedded-hal-nb = "=1.0.0-alpha.1"
 log = { path = "../../../../lib/log" }
 nb = "1"
 riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }

diff --git a/src/mainboard/sipeed/m1s-dock/e907/src/init.rs b/src/mainboard/sipeed/m1s-dock/e907/src/init.rs
@@ -6,7 +6,6 @@ const CPU_RST: u32 = 1 << 1;
 
 pub const MM_BASE: usize = 0x3000_0000;
 
-
 const MM_GLB_BASE: usize = 0x3000_7000;
 const MM_SYS_CTRL: usize = MM_GLB_BASE;
 const MM_SW_SYS_RESET: usize = MM_GLB_BASE + 0x0040;

diff --git a/src/mainboard/sipeed/m1s-dock/e907/src/main.rs b/src/mainboard/sipeed/m1s-dock/e907/src/main.rs
@@ -116,10 +116,10 @@ fn main() {
     let glb = p.GLB;
     init::gpio_uart_init(&glb);
     let serial = uart::BSerial::new(p.UART0, p.UART1);
-    init_logger(serial);
-
     // print to UART0
-    log::debug('*' as u8);
+    serial.debug('*' as u8);
+
+    init_logger(serial);
 
     // prints to UART1
     println!("oreboot 🦀");
@@ -183,8 +183,8 @@ fn main() {
     // NOTE: before using PSRAM, also implement PHY init; see Bl808 SDK
     // drivers/bl808_driver/std_drv/src/bl808_uhs_phy.c
 
-    unsafe { write_volatile(PSRAM_BASE as *mut u32, 0x1234_5678) }
-    dump(PSRAM_BASE, 8);
+    // unsafe { write_volatile(PSRAM_BASE as *mut u32, 0x1234_5678) }
+    // dump(PSRAM_BASE, 8);
 
     init::resume_mm(MM_ENTRY as u32);
     if false {

diff --git a/src/mainboard/sipeed/m1s-dock/e907/src/uart.rs b/src/mainboard/sipeed/m1s-dock/e907/src/uart.rs
@@ -38,19 +38,19 @@ impl BSerial {
             .write(|w| w.transmit().variant(txp).receive().variant(rxp));
         Self { u0, u1 }
     }
-}
 
-impl Serial for BSerial {
-    fn debug(&self, num: u8) {
+    pub fn debug(&self, num: u8) {
         self.u0.data_write.write(|w| w.value().variant(num));
     }
 }
 
+impl Serial for BSerial {}
+
 impl embedded_hal::serial::ErrorType for BSerial {
     type Error = Error;
 }
 
-impl embedded_hal::serial::nb::Write<u8> for BSerial {
+impl embedded_hal_nb::serial::Write<u8> for BSerial {
     #[inline]
     fn write(&mut self, c: u8) -> nb::Result<(), self::Error> {
         if self.u1.bus_state.read().transmit_busy().is_busy() {