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## Copyright (C) 2021 Andrius Štikonas | ||
## This file is part of M2-Planet. | ||
## | ||
## M2-Planet is free software: you can redistribute it and/or modify | ||
## it under the terms of the GNU General Public License as published by | ||
## the Free Software Foundation, either version 3 of the License, or | ||
## (at your option) any later version. | ||
## | ||
## M2-Planet is distributed in the hope that it will be useful, | ||
## but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
## GNU General Public License for more details. | ||
## | ||
## You should have received a copy of the GNU General Public License | ||
## along with M2-Planet. If not, see <http://www.gnu.org/licenses/>. | ||
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;; Used to terminate word | ||
DEFINE NULL 00000000 | ||
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;; Opcodes | ||
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;; RV32I Base Instruction Set | ||
DEFINE LUI 00000037 | ||
DEFINE AUIPC 00000017 | ||
DEFINE JAL 0000006F | ||
DEFINE JALR 00000067 | ||
DEFINE BEQ 00000063 | ||
DEFINE BNE 00001063 | ||
DEFINE BLT 00004063 | ||
DEFINE BGE 00005063 | ||
DEFINE BLTU 00006063 | ||
DEFINE BGEU 00007063 | ||
DEFINE LB 00000003 | ||
DEFINE LH 00001003 | ||
DEFINE LW 00002003 | ||
DEFINE LBU 00004003 | ||
DEFINE LHU 00005003 | ||
DEFINE SB 00000023 | ||
DEFINE SH 00001023 | ||
DEFINE SW 00002023 | ||
DEFINE ADDI 00000013 | ||
DEFINE SLTI 00002013 | ||
DEFINE SLTIU 00003013 | ||
DEFINE XORI 00004013 | ||
DEFINE ORI 00006013 | ||
DEFINE ANDI 00007013 | ||
DEFINE SLLI 00001013 | ||
DEFINE SRLI 00005013 | ||
DEFINE SRAI 40005013 | ||
DEFINE ADD 00000033 | ||
DEFINE SUB 40000033 | ||
DEFINE SLL 00001033 | ||
DEFINE SLT 00002033 | ||
DEFINE SLTU 00003033 | ||
DEFINE XOR 00004033 | ||
DEFINE SRL 00005033 | ||
DEFINE SRA 40005033 | ||
DEFINE OR 00006033 | ||
DEFINE AND 00007033 | ||
DEFINE ECALL 00000073 | ||
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;; RV64I Base Instruction set | ||
DEFINE LWU 00006003 | ||
DEFINE LD 00003003 | ||
DEFINE SD 00003023 | ||
DEFINE ADDIW 0000001B | ||
DEFINE SLLI 0000101B | ||
DEFINE SRLI 0000501B | ||
DEFINE SRAI 4000501B | ||
DEFINE ADDW 0000003B | ||
DEFINE SUBW 4000003B | ||
DEFINE SLLW 0000103B | ||
DEFINE SRL 0000503B | ||
DEFINE SRAW 4000503B | ||
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;; Pseudoinstructions | ||
DEFINE NOP 00000013 # ADDI | ||
DEFINE MV 00000013 # ADDI | ||
DEFINE NOT FFF04013 # XORI, RD, RS, -1 | ||
DEFINE BEQZ 00000063 # BEQ | ||
DEFINE BNEZ 00001063 # BNE | ||
DEFINE BLTZ 00004063 # BLT | ||
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;; Destination registers | ||
;; register_number << 7 | ||
DEFINE RD_RA .00000080 | ||
DEFINE RD_SP .00000100 | ||
DEFINE RD_GP .00000180 | ||
DEFINE RD_TP .00000200 | ||
DEFINE RD_T0 .00000280 | ||
DEFINE RD_T1 .00000300 | ||
DEFINE RD_T2 .00000380 | ||
DEFINE RD_S0 .00000400 | ||
DEFINE RD_S1 .00000480 | ||
DEFINE RD_A0 .00000500 | ||
DEFINE RD_A1 .00000580 | ||
DEFINE RD_A2 .00000600 | ||
DEFINE RD_A3 .00000680 | ||
DEFINE RD_A4 .00000700 | ||
DEFINE RD_A5 .00000780 | ||
DEFINE RD_A6 .00000800 | ||
DEFINE RD_A7 .00000880 | ||
DEFINE RD_S2 .00000900 | ||
DEFINE RD_S3 .00000980 | ||
DEFINE RD_S4 .00000A00 | ||
DEFINE RD_S5 .00000A80 | ||
DEFINE RD_S6 .00000B00 | ||
DEFINE RD_S7 .00000B80 | ||
DEFINE RD_S8 .00000C00 | ||
DEFINE RD_S9 .00000C80 | ||
DEFINE RD_S10 .00000D00 | ||
DEFINE RD_S11 .00000D80 | ||
DEFINE RD_T3 .00000E00 | ||
DEFINE RD_T4 .00000E80 | ||
DEFINE RD_T5 .00000F00 | ||
DEFINE RD_T6 .00000F80 | ||
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;; First source registers | ||
;; register_number << 15 | ||
DEFINE RS1_RA .00008000 | ||
DEFINE RS1_SP .00010000 | ||
DEFINE RS1_GP .00018000 | ||
DEFINE RS1_TP .00020000 | ||
DEFINE RS1_T0 .00028000 | ||
DEFINE RS1_T1 .00030000 | ||
DEFINE RS1_T2 .00038000 | ||
DEFINE RS1_S0 .00040000 | ||
DEFINE RS1_S1 .00048000 | ||
DEFINE RS1_A0 .00050000 | ||
DEFINE RS1_A1 .00058000 | ||
DEFINE RS1_A2 .00060000 | ||
DEFINE RS1_A3 .00068000 | ||
DEFINE RS1_A4 .00070000 | ||
DEFINE RS1_A5 .00078000 | ||
DEFINE RS1_A6 .00080000 | ||
DEFINE RS1_A7 .00088000 | ||
DEFINE RS1_S2 .00090000 | ||
DEFINE RS1_S3 .00098000 | ||
DEFINE RS1_S4 .000A0000 | ||
DEFINE RS1_S5 .000A8000 | ||
DEFINE RS1_S6 .000B0000 | ||
DEFINE RS1_S7 .000B8000 | ||
DEFINE RS1_S8 .000C0000 | ||
DEFINE RS1_S9 .000C8000 | ||
DEFINE RS1_S10 .000D0000 | ||
DEFINE RS1_S11 .000D8000 | ||
DEFINE RS1_T3 .000E0000 | ||
DEFINE RS1_T4 .000E8000 | ||
DEFINE RS1_T5 .000F0000 | ||
DEFINE RS1_T6 .000F8000 | ||
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;; Second source registers | ||
;; register_number << 20 | ||
DEFINE RS2_RA .00100000 | ||
DEFINE RS2_SP .00200000 | ||
DEFINE RS2_GP .00300000 | ||
DEFINE RS2_TP .00400000 | ||
DEFINE RS2_T0 .00500000 | ||
DEFINE RS2_T1 .00600000 | ||
DEFINE RS2_T2 .00700000 | ||
DEFINE RS2_S0 .00800000 | ||
DEFINE RS2_S1 .00900000 | ||
DEFINE RS2_A0 .00A00000 | ||
DEFINE RS2_A1 .00B00000 | ||
DEFINE RS2_A2 .00C00000 | ||
DEFINE RS2_A3 .00D00000 | ||
DEFINE RS2_A4 .00E00000 | ||
DEFINE RS2_A5 .00F00000 | ||
DEFINE RS2_A6 .01000000 | ||
DEFINE RS2_A7 .01100000 | ||
DEFINE RS2_S2 .01200000 | ||
DEFINE RS2_S3 .01300000 | ||
DEFINE RS2_S4 .01400000 | ||
DEFINE RS2_S5 .01500000 | ||
DEFINE RS2_S6 .01600000 | ||
DEFINE RS2_S7 .01700000 | ||
DEFINE RS2_S8 .01800000 | ||
DEFINE RS2_S9 .01900000 | ||
DEFINE RS2_S10 .01A00000 | ||
DEFINE RS2_S11 .01B00000 | ||
DEFINE RS2_T3 .01C00000 | ||
DEFINE RS2_T4 .01D00000 | ||
DEFINE RS2_T5 .01E00000 | ||
DEFINE RS2_T6 .01F00000 |