Verilator flags (#1628)

os-fpga · Jun 26, 2024 · 92f77e8 · 92f77e8
1 parent 6b7e3d6
commit 92f77e8
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/src/Simulation/Simulator.cpp b/src/Simulation/Simulator.cpp
@@ -545,7 +545,8 @@ std::string Simulator::SimulatorCompilationOptions(SimulationType simulation,
           "-cc --assert -Wall -Wno-DECLFILENAME "
           "-Wno-UNUSEDSIGNAL "
           "-Wno-TIMESCALEMOD "
-          "-Wno-WIDTH -Wno-fatal -Wno-BLKANDNBLK ";
+          "-Wno-WIDTH -Wno-fatal -Wno-BLKANDNBLK -Wno-BLKLOOPINIT "
+          "-Wno-MULTIDRIVEN -DSIM_VERILATOR";
       if (simulation == SimulationType::PNR ||
           simulation == SimulationType::Gate)
         options += "--timing ";