feat(vfpu): add missing instructions + prefix support (C000[X,Y,Z])

[SK83RJOSH]

I generated most of the missing instructions using a tool I created and have confirmed the accuracy of the code gen via tests I'm writing for a vector math library. Though it would be wise to do a regression test of this commit against the rust-psp samples. 🙂

This table details the supported instructions, including their encoding/parameter formats for convenience. Anything not supported is likely best to be hand-rolled from this point on.

Instruction Support (99/113)

?	Inst	Ops	Enc
⬜	bvf	vfpu-branch	vfpu-branch
⬜	bvfl	vfpu-branch	vfpu-branch
⬜	bvt	vfpu-branch	vfpu-branch
⬜	bvtl	vfpu-branch	vfpu-branch
✅	lv.q	vfpu-load16	vfpu-memory-quad
✅	lv.s	vfpu-load4	vfpu-memory
⬜	lvl.q	vfpu-load16	vfpu-memory-quad
⬜	lvr.q	vfpu-load16	vfpu-memory-quad
✅	mfvc	vfpu-control-gpr	vfpu-gpr-control
✅	mtvc	vfpu-control-gpr	vfpu-gpr-control
✅	sv.q	vfpu-store16	vfpu-memory-quad
✅	sv.s	vfpu-store4	vfpu-memory
⬜	svl.q	vfpu-store16	vfpu-memory-quad
⬜	svr.q	vfpu-store16	vfpu-memory-quad
✅	vabs	vector-unary	vfpu-alu
✅	vadd	vector-binary	vfpu-alu
✅	vasin	vector-unary	vfpu-alu
✅	vavg	vector-unary-reduce	vfpu-alu
✅	vbfy1	vector-unary	vfpu-alu
✅	vbfy2	vector-unary	vfpu-alu
✅	vc2i	vector-unary-expand4	vfpu-alu
⬜	vcmovf	vfpu-condmove	vfpu-condmove
⬜	vcmovt	vfpu-condmove	vfpu-condmove
⬜	vcmp	vfpu-compare	vfpu-alu-compare
✅	vcos	vector-unary	vfpu-alu
✅	vcrs	vector-binary	vfpu-alu
✅	vcrsp	vector-binary	vfpu-alu
✅	vcst	vector-nullary-cst	vector-imm5
✅	vdet	vector-binary-reduce	vfpu-alu
✅	vdiv	vector-binary	vfpu-alu
✅	vdot	vector-binary-reduce	vfpu-alu
✅	vexp2	vector-unary	vfpu-alu
✅	vf2h	vector-unary-reduce2	vfpu-alu
✅	vf2id	vector-unary-scale	vector-imm5
✅	vf2in	vector-unary-scale	vector-imm5
✅	vf2iu	vector-unary-scale	vector-imm5
✅	vf2iz	vector-unary-scale	vector-imm5
✅	vfad	vector-unary-reduce	vfpu-alu
✅	vfim	vector-nullary-uimm16	vector-imm16
✅	vflush	vfpu-static	vfpu-fixedop
✅	vh2f	vector-unary-expand2	vfpu-alu
✅	vhdp	vector-binary-reduce	vfpu-alu
✅	vhtfm2	vector-matrix-transform	vfpu-alu-m1
✅	vhtfm3	vector-matrix-transform	vfpu-alu-m1
✅	vhtfm4	vector-matrix-transform	vfpu-alu-m1
✅	vi2c	vector-unary-reduce	vfpu-alu
✅	vi2f	vector-unary-scale	vector-imm5
✅	vi2s	vector-unary-reduce2	vfpu-alu
✅	vi2uc	vector-unary-reduce	vfpu-alu
✅	vi2us	vector-unary-reduce2	vfpu-alu
✅	vidt	vector-nullary	vfpu-alu
✅	viim	vector-nullary-uimm16	vector-imm16
✅	vlgb	vector-unary	vfpu-alu
✅	vlog2	vector-unary	vfpu-alu
✅	vmax	vector-binary	vfpu-alu
⬜	vmfvc	vfpu-control-read	vfpu-read-control
✅	vmidt	matrix-nullary	vfpu-alu
✅	vmin	vector-binary	vfpu-alu
✅	vmmov	matrix-unary	vfpu-alu
✅	vmmul	matrix-binary	vfpu-alu
✅	vmone	matrix-nullary	vfpu-alu
✅	vmov	vector-unary	vfpu-alu
✅	vmscl	matrix-binary-scale	vfpu-alu
⬜	vmtvc	vfpu-control-write	vfpu-write-control
✅	vmul	vector-binary	vfpu-alu
✅	vmzero	matrix-nullary	vfpu-alu
✅	vneg	vector-unary	vfpu-alu
✅	vnop	vfpu-static	vfpu-fixedop
✅	vnrcp	vector-unary	vfpu-alu
✅	vnsin	vector-unary	vfpu-alu
✅	vocp	vector-unary	vfpu-alu
✅	vone	vector-nullary	vfpu-alu
✅	vpfxd	vfpu-prefix	vfpu-prefix
✅	vpfxs	vfpu-prefix	vfpu-prefix
✅	vpfxt	vfpu-prefix	vfpu-prefix
✅	vqmul	vector-binary	vfpu-alu
✅	vrcp	vector-unary	vfpu-alu
✅	vrexp2	vector-unary	vfpu-alu
✅	vrndf1	vector-nullary	vfpu-alu
✅	vrndf2	vector-nullary	vfpu-alu
✅	vrndi	vector-nullary	vfpu-alu
✅	vrnds	vector-inullary	vfpu-alu
✅	vrot	vector-unary-rot	vector-imm5
✅	vrsq	vector-unary	vfpu-alu
✅	vs2i	vector-unary-expand2	vfpu-alu
✅	vsat0	vector-unary	vfpu-alu
✅	vsat1	vector-unary	vfpu-alu
✅	vsbn	vector-binary	vfpu-alu
✅	vsbz	vector-unary	vfpu-alu
✅	vscl	vector-binary-scale	vfpu-alu
✅	vscmp	vector-binary	vfpu-alu
✅	vsge	vector-binary	vfpu-alu
✅	vsgn	vector-unary	vfpu-alu
✅	vsin	vector-unary	vfpu-alu
✅	vslt	vector-binary	vfpu-alu
✅	vsocp	vector-unary-expand2	vfpu-alu
✅	vsqrt	vector-unary	vfpu-alu
✅	vsrt1	vector-unary	vfpu-alu
✅	vsrt2	vector-unary	vfpu-alu
✅	vsrt3	vector-unary	vfpu-alu
✅	vsrt4	vector-unary	vfpu-alu
✅	vsub	vector-binary	vfpu-alu
✅	vsync	vfpu-static	vfpu-fixedop
✅	vt4444	vector-unary-reduce2	vfpu-alu
✅	vt5551	vector-unary-reduce2	vfpu-alu
✅	vt5650	vector-unary-reduce2	vfpu-alu
✅	vtfm2	vector-matrix-transform	vfpu-alu
✅	vtfm3	vector-matrix-transform	vfpu-alu
✅	vtfm4	vector-matrix-transform	vfpu-alu
✅	vuc2ifs	vector-unary-expand4	vfpu-alu
✅	vus2i	vector-unary-expand2	vfpu-alu
⬜	vwbn	vector-unary-mod	vector-imm8
✅	vzero	vector-nullary	vfpu-alu

[SK83RJOSH]

@sajattack this would close #63, and we should create a new issue tracking the missing instructions :)

[SK83RJOSH]

I would also like to add that there's a possibility of implementing swizzling to all supported instructions, but it would require an additional TT muncher, or an additional macro that supports all combinations of: X, |X|, -|X|

I wasn't clever enough to do the muncher, and the latter would be a combinatorial explosion. I figured Saj or Potato might be better at macros though, so if either of you can come up with a clever way to do it I can go ahead and do another round of codegen.

EDIT: You already had a muncher for this, added prefix support to all arguments that support it :)

[SK83RJOSH]

@overdrivenpotato I think this PR is ready for review, if you'd do me the honors ❤️

[sajattack]

@SK83RJOSH
VFPU math tests (using vsin and vcos) are failing
https://ci.mijalkovic.ca/teams/rust-psp/pipelines/rust-psp/jobs/run-tests-for-pr/builds/409.2

rust-psp/psp/src/math/mod.rs

Lines 61 to 99 in 693423a

	#[no_mangle]
	pub unsafe extern "C" fn cosf(scalar: f32) -> f32 {
	let out: f32;
	vfpu_asm! (
	"mfc1 {tmp}, {scalar}",
	"mtv {tmp}, S000",
	"nop",
	"vcst.s S001, VFPU_2_PI",
	"vmul.s S000, S000, S001",
	"vcos.s S000, S000",
	"mfv {tmp}, S000",
	"mtc1 {tmp}, {scalar}",
	"nop",
	scalar = inlateout(freg) scalar => out,
	tmp = out(reg) _,
	options(nostack, nomem),
	);
	out
	}
	#[no_mangle]
	pub unsafe extern "C" fn sinf(scalar: f32) -> f32 {
	let out: f32;
	vfpu_asm! (
	"mfc1 {tmp}, {scalar}",
	"mtv {tmp}, S000",
	"nop",
	"vcst.s S001, VFPU_2_PI",
	"vmul.s S000, S000, S001",
	"vsin.s S000, S000",
	"mfv {tmp}, S000",
	"mtc1 {tmp}, {scalar}",
	"nop",
	scalar = inlateout(freg) scalar => out,
	tmp = out(reg) _,
	options(nostack, nomem),
	);
	out
	}

https://github.com/overdrivenpotato/rust-psp/blob/master/ci/tests/src/math_test.rs

[davidgfnet]

BTW you could use the automated test generator at https://github.com/pspdev/vfpu-docs/ to generate your tests. It would need to be modified to output Rust code, but seems doable to me :)
Just my 2c really, I really hate writing tests so I only wrote a small subset of them (the ones that take more time to automate than just manually write).

[SK83RJOSH]

My plan was to try to write tests for a few instructions of each encoding + each of their flavors; since I think that should be rigorous enough for all codegen but I'll most definitely take a look at that. 🙏

Ironically enough, this entire thing has lead me down another rabbit hole atm, which is getting assertions/stack traces working correctly so I can make the user story for testing a bit less cumbersome... though after a week of plugging away at that I may have to accept what we have 😄

[SK83RJOSH]

Alrighty, added tests that should hit most if not all of the code gen, with the exception of fixedop + imm16 since those are pretty straight forward/are near identical to other instructions. The only thing I have tested here, that I would like to, is matrix operations.

Hold off on merging this until I can validate those, since it would be very unfortunate if gum breaks.

Okey-dokey, I tested the samples + my own project for regressions in gum, only found one so this should be ready to merge. 🙂