common/mlx5: add DevX command to query WQ

Add a DevX command to query Rx queues attributes created by VERBS.

Currently support only counter_set_id attribute.

This counter ID is managed by the kernel driver and being assigned to
any queue created by the kernel.

Cc: stable@dpdk.org

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

drivers/common/mlx5/mlx5_devx_cmds.c

@@ -2165,3 +2165,31 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
 	return geneve_tlv_opt_obj;
 }
 
+int
+mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
+{
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+	uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
+	uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
+	int rc;
+	void *rq_ctx;
+
+	MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
+	MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
+	rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
+	if (rc) {
+		rte_errno = errno;
+		DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
+			"rc = %d, errno = %d.", rc, errno);
+		return -rc;
+	};
+	rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
+	*counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
+	return 0;
+#else
+	(void)wq;
+	(void)counter_set_id;
+	return -ENOTSUP;
+#endif
+}
+

drivers/common/mlx5/mlx5_devx_cmds.h

@@ -539,4 +539,7 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
 
 __rte_internal
 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
+
+__rte_internal
+int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */

drivers/common/mlx5/mlx5_prm.h

@@ -911,6 +911,7 @@ enum {
 	MLX5_CMD_OP_MODIFY_SQ = 0X905,
 	MLX5_CMD_OP_CREATE_RQ = 0x908,
 	MLX5_CMD_OP_MODIFY_RQ = 0x909,
+	MLX5_CMD_OP_QUERY_RQ = 0x90b,
 	MLX5_CMD_OP_CREATE_TIS = 0x912,
 	MLX5_CMD_OP_QUERY_TIS = 0x915,
 	MLX5_CMD_OP_CREATE_RQT = 0x916,
@@ -1890,6 +1891,24 @@ struct mlx5_ifc_modify_rq_out_bits {
 	u8 reserved_at_40[0x40];
 };
 
+struct mlx5_ifc_query_rq_out_bits {
+	u8 status[0x8];
+	u8 reserved_at_8[0x18];
+	u8 syndrome[0x20];
+	u8 reserved_at_40[0xc0];
+	struct mlx5_ifc_rqc_bits rq_context;
+};
+
+struct mlx5_ifc_query_rq_in_bits {
+	u8 opcode[0x10];
+	u8 reserved_at_10[0x10];
+	u8 reserved_at_20[0x10];
+	u8 op_mod[0x10];
+	u8 reserved_at_40[0x8];
+	u8 rqn[0x18];
+	u8 reserved_at_60[0x20];
+};
+
 struct mlx5_ifc_create_tis_out_bits {
 	u8 status[0x8];
 	u8 reserved_at_8[0x18];

drivers/common/mlx5/version.map

@@ -41,6 +41,7 @@ INTERNAL {
 	mlx5_devx_cmd_query_virtio_q_counters;
 	mlx5_devx_cmd_query_virtq;
 	mlx5_devx_cmd_register_read;
+	mlx5_devx_cmd_wq_query;
 	mlx5_devx_get_out_command_status;
 	mlx5_devx_alloc_uar;