Add Sidecar front IO HSC control, work around front IO PHY oscillator errata #1449
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… errata The oscillator used to drive the VSC8562 PHY on the Sidecar front IO board occasionally fails to start properly, causing the QSGMII link to the management network switch to fail and the technician ports to be non-functional. This diff does the following: - Implement sequencer control over the front IO hot swap controller - Make monorail-server detect the oscillator failure, request a power cycle of the front IO board and retry PHY initialization until the QSGMII link is operational - Refactor power rail status primitives into a new `fpga-app-api` crate
arjenroodselaar
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drv/fpga-app-api/src/power_rail.rs
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| /// This module implements state primitives matching the generic power | ||
| /// rail/voltage regulator as implemented in | ||
| /// https://github.com/oxidecomputer/quartz/blob/main/hdl/power_rail.rdl, | ||
| /// https://github.com/oxidecomputer/quartz/blob/main/hdl/PowerRail.bsv. |
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We have a pattern to tightly integrate types defined via RDL into our BSV/Rust code. At first blush, leaning on that could easily eliminate the duplicate hand coding of the PowerRailStatus enum. I don't recall if we support generating structs off hand, so PowerFailPinState may not be covered but that seems like a natural place to continue to expand our integration here lest we need to change RDL, BSV, and Rust every time a register changes.
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Yes, the reason this looks the way it does is because while RDL can define types, we currently can't export those types through the JSON representation into Hubris. We can only generate specific instantiations of that type within a register map. We should figure out how to extend our capabilities here, but I don't want to hold up this diff on something open-ended.
The oscillator used to drive the VSC8562 PHY on the Sidecar front IO board occasionally fails to start properly, causing the QSGMII link to the management network switch to fail and the technician ports to be non-functional (#1410). This diff does the following:
fpga-app-apicrate