Enable EXTI interrupt dispatch support in stm32xx-sys #1691
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hawkw
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Mar 28, 2024
hawkw
reviewed
Mar 28, 2024
drv/stm32xx-sys/src/main.rs
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| // It's really tempting to try and not do this test on every | ||
| // loop iteration, isn't it? Too bad, these registers all | ||
| // have totally distinct types because of the PAC. | ||
| match register { | ||
| 0 => syscfg.exticr1.modify(|_, w| match slot { | ||
| // Safety: field modeled incorrectly in PAC | ||
| 0 => unsafe { w.exti0().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 1 => unsafe { w.exti1().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 2 => unsafe { w.exti2().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| _ => unsafe { w.exti3().bits(port as u8) }, | ||
| }), | ||
| 1 => syscfg.exticr2.modify(|_, w| match slot { | ||
| // Safety: field modeled incorrectly in PAC | ||
| 0 => unsafe { w.exti4().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 1 => unsafe { w.exti5().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 2 => unsafe { w.exti6().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| _ => unsafe { w.exti7().bits(port as u8) }, | ||
| }), | ||
| 2 => syscfg.exticr3.modify(|_, w| match slot { | ||
| // Safety: field modeled incorrectly in PAC | ||
| 0 => unsafe { w.exti8().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 1 => unsafe { w.exti9().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 2 => unsafe { w.exti10().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| _ => unsafe { w.exti11().bits(port as u8) }, | ||
| }), | ||
| _ => syscfg.exticr4.modify(|_, w| match slot { | ||
| // Safety: field modeled incorrectly in PAC | ||
| 0 => unsafe { w.exti12().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 1 => unsafe { w.exti13().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| 2 => unsafe { w.exti14().bits(port as u8) }, | ||
| // Safety: field modeled incorrectly in PAC | ||
| _ => unsafe { w.exti15().bits(port as u8) }, | ||
| }), | ||
| } |
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this whole block of code really makes me feel very positively about the PAC :/
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Fortunately if we want to fix how the fields are modeled, all we have to do is construct a YAML file describing a diff we want to apply to another YAML file derived from an XML file that isn't checked into the repo.
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Sooooo I'm honestly kind of shocked that this didn't blow size allocations on the stm32g0 builds, but it does not appear to have done so. I think this is ready for review. |
hawkw
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Rebased and applied requested fixes. Also expanded the docs a bit. (Still want to put docs somewhere other than the driver source code, but haven't done that yet.) |
This adds a slightly-hacked-up EXTI driver for STM32H7. It is currently statically configured to deliver interrupts from one pin to one task, because that's what we initially needed. We are going to improve this.
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This was referenced Apr 1, 2024
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This adds code to
systo multiplex the frustratingly limited STM32 EXTI peripheral and provide arbitrary pin change interrupts to other tasks.We're doing this in support of a Gimlet racktest debugging operation, and so this version is deliberately a bit limited. It will, in practice, only build in gimlet or sidecar, and will only watch PI14, and will only post a specific notification to the power task. @hawkw is working on making all that stuff configurable in parallel to my work.
For this to be useful, the power task needs to follow the instructions in the Theory Of Operation comment I've added to
drv/stm32xx-sys/src/main.rs.