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->Verilog made easy ->Interview day verilog revision

Name		Name	Last commit message	Last commit date
Latest commit History 28 Commits
Edaplayground/memory		Edaplayground/memory
Both_Edge_detect.v		Both_Edge_detect.v
D_latch.v		D_latch.v
Dualedge_FF.v		Dualedge_FF.v
Mealey_101sequence.v		Mealey_101sequence.v
Moore_FSM.v		Moore_FSM.v
Moore_FSM_comb_onehot.v		Moore_FSM_comb_onehot.v
Moore_FSM_combinational.v		Moore_FSM_combinational.v
Multiple_Clock_divider.v		Multiple_Clock_divider.v
Negedge_capture_stay_till_rst.v		Negedge_capture_stay_till_rst.v
Parameters.v		Parameters.v
README.md		README.md
Sensitivity_list.v		Sensitivity_list.v
Task_vs_function.v		Task_vs_function.v
arithmetic_shift.v		arithmetic_shift.v
async_FIFO.v		async_FIFO.v
generate.v		generate.v
load_rotate_100inputs.v		load_rotate_100inputs.v
sync_FIFO.v		sync_FIFO.v

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