aliased image, but progress

src/pwh_lab/rh_video_display/_ngo/netlist.lst

@@ -1,6 +1,9 @@
-/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/lab3.ngc 1354773273
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/lab3.ngc 1354860337
 /afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/lotr_song.ngc 1354590940
 /afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/song_scales.ngc 1354591515
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/bono_blue.ngc 1354855227
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/bono_red.ngc 1354855283
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/bono_green.ngc 1354855344
 /afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/font_rom.edn 1354240031
 /afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display/note_letters_bmp.ngc 1354243692
 OK

src/pwh_lab/rh_video_display/_xmsgs/par.xmsgs

@@ -851,7 +851,7 @@
 <msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">user4&lt;9&gt;_IBUF</arg> has no load.  PAR will not attempt to route this signal.
 </msg>
 
-<msg type="info" file="Place" num="834" delta="unknown" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">541</arg> IOs, <arg fmt="%d" index="2">540</arg> are locked and <arg fmt="%d" index="3">1</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> 
+<msg type="info" file="Place" num="834" delta="unknown" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">576</arg> IOs, <arg fmt="%d" index="2">575</arg> are locked and <arg fmt="%d" index="3">1</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> 
 </msg>
 
 <msg type="info" file="Timing" num="2761" delta="unknown" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>

src/pwh_lab/rh_video_display/bono_blue.sym

@@ -1,7 +1,7 @@
 VERSION 5
 BEGIN SYMBOL bono_blue
 SYMBOLTYPE BLOCK
-TIMESTAMP 2012 12 5 20 24 34
+TIMESTAMP 2012 12 7 4 40 4
 SYMPIN 0 80 Input addra[7:0]
 SYMPIN 0 272 Input clka
 SYMPIN 576 80 Output douta[7:0]

src/pwh_lab/rh_video_display/bono_blue_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt

@@ -5,7 +5,7 @@
     The structure and the elements are likely to change over the next few releases.
     This means code written to parse this file will need to be revisited each subsequent release.-->
 
-  <application stringID="Xst" timeStamp="Wed Dec  5 15:24:37 2012">
+  <application stringID="Xst" timeStamp="Thu Dec  6 23:40:09 2012">
     <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_PARTITION_REPORT">

src/pwh_lab/rh_video_display/bono_blue_readme.txt

@@ -0,0 +1,61 @@
+The following files were generated for 'bono_blue' in directory 
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display:
+
+bono_blue.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+bono_blue.mif:
+   Memory Initialization File which is automatically generated by the
+   CORE Generator System for some modules when a simulation flow is
+   specified. A MIF data file is used to support HDL functional
+   simulation of modules which use arrays of values.
+
+bono_blue.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+bono_blue.sym:
+   Please see the core data sheet.
+
+bono_blue.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+bono_blue.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+bono_blue.vhd:
+   VHDL wrapper file provided to support functional simulation. This
+   file contains simulation model customization data that is passed to
+   a parameterized simulation model for the core.
+
+bono_blue.vho:
+   VHO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a VHDL design.
+
+bono_blue.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+bono_blue_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+bono_blue_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+bono_blue_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+bono_blue_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+

src/pwh_lab/rh_video_display/bono_green.sym

@@ -1,7 +1,7 @@
 VERSION 5
 BEGIN SYMBOL bono_green
 SYMBOLTYPE BLOCK
-TIMESTAMP 2012 12 5 20 23 36
+TIMESTAMP 2012 12 7 4 42 1
 SYMPIN 0 80 Input addra[7:0]
 SYMPIN 0 272 Input clka
 SYMPIN 576 80 Output douta[7:0]

src/pwh_lab/rh_video_display/bono_green_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt

@@ -5,7 +5,7 @@
     The structure and the elements are likely to change over the next few releases.
     This means code written to parse this file will need to be revisited each subsequent release.-->
 
-  <application stringID="Xst" timeStamp="Wed Dec  5 15:23:39 2012">
+  <application stringID="Xst" timeStamp="Thu Dec  6 23:42:04 2012">
     <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_PARTITION_REPORT">

src/pwh_lab/rh_video_display/bono_green_readme.txt

@@ -0,0 +1,61 @@
+The following files were generated for 'bono_green' in directory 
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display:
+
+bono_green.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+bono_green.mif:
+   Memory Initialization File which is automatically generated by the
+   CORE Generator System for some modules when a simulation flow is
+   specified. A MIF data file is used to support HDL functional
+   simulation of modules which use arrays of values.
+
+bono_green.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+bono_green.sym:
+   Please see the core data sheet.
+
+bono_green.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+bono_green.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+bono_green.vhd:
+   VHDL wrapper file provided to support functional simulation. This
+   file contains simulation model customization data that is passed to
+   a parameterized simulation model for the core.
+
+bono_green.vho:
+   VHO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a VHDL design.
+
+bono_green.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+bono_green_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+bono_green_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+bono_green_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+bono_green_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+

src/pwh_lab/rh_video_display/bono_pb.v

@@ -9,10 +9,11 @@ module bono_picture_blob
 	(input pixel_clk,
 	input [10:0] x,hcount,
 	input [9:0] y,vcount,
+	input [7:0] image_bits,
 	output reg [23:0] pixel);
 
 	wire [19:0] image_addr; // num of bits for 20 
-	wire [7:0] image_bits, red_mapped, green_mapped, blue_mapped;
+	wire [7:0] red_mapped, green_mapped, blue_mapped;
 	// note the one clock cycle delay in pixel!
 	always @ (posedge pixel_clk) begin
 		if ((hcount >= x && hcount < (x+WIDTH)) &&
@@ -22,12 +23,14 @@ module bono_picture_blob
 	end
 
 	// calculate rom address and read the location
-	assign image_addr = (hcount-x) + (vcount-y) * WIDTH;
+	//assign image_addr = (hcount-x) + (vcount-y) * WIDTH;
 	//bono_pixels b_rom(pixel_clk, image_addr, image_bits);
-
-	bono_blue b_blue(image_bits, pixel_clk, blue_mapped);
-	bono_red b_red(image_bits, pixel_clk, red_mapped);
-	bono_green b_green(image_bits, pixel_clk, green_mapped);
+	bono_blue b_blue(.clka(pixel_clk),.addra(image_bits),
+						   .douta(blue_mapped));
+	bono_red b_red(.clka(pixel_clk),.addra(image_bits),
+						.douta(red_mapped));
+	bono_green b_green(.clka(pixel_clk),.addra(image_bits), 
+							 .douta(green_mapped));
 endmodule
 
 

src/pwh_lab/rh_video_display/bono_picture_blob.prj

@@ -0,0 +1,4 @@
+verilog work "bono_red.v"
+verilog work "bono_green.v"
+verilog work "bono_blue.v"
+verilog work "bono_pb.v"

src/pwh_lab/rh_video_display/bono_picture_blob.stx

@@ -0,0 +1,39 @@
+Release 10.1.03 - xst K.39 (lin64)
+Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+--> 
+Parameter TMPDIR set to ./xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.05 secs
+
+--> 
+
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling verilog file "bono_red.v" in library work
+Compiling verilog file "bono_green.v" in library work
+Module <bono_red> compiled
+Compiling verilog file "bono_blue.v" in library work
+Module <bono_green> compiled
+Compiling verilog file "bono_pb.v" in library work
+Module <bono_blue> compiled
+Module <bono_picture_blob> compiled
+No errors in compilation
+Analysis of file <"bono_picture_blob.prj"> succeeded.
+
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.08 secs
+
+--> 
+
+
+Total memory usage is 283576 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+

src/pwh_lab/rh_video_display/bono_picture_blob.xst

@@ -0,0 +1,4 @@
+set -tmpdir "./xst/projnav.tmp"
+elaborate
+-ifn bono_picture_blob.prj
+-ifmt mixed

src/pwh_lab/rh_video_display/bono_red.sym

@@ -1,7 +1,7 @@
 VERSION 5
 BEGIN SYMBOL bono_red
 SYMBOLTYPE BLOCK
-TIMESTAMP 2012 12 5 20 22 31
+TIMESTAMP 2012 12 7 4 41 1
 SYMPIN 0 80 Input addra[7:0]
 SYMPIN 0 272 Input clka
 SYMPIN 576 80 Output douta[7:0]

src/pwh_lab/rh_video_display/bono_red_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt

@@ -5,7 +5,7 @@
     The structure and the elements are likely to change over the next few releases.
     This means code written to parse this file will need to be revisited each subsequent release.-->
 
-  <application stringID="Xst" timeStamp="Wed Dec  5 15:22:38 2012">
+  <application stringID="Xst" timeStamp="Thu Dec  6 23:41:04 2012">
     <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_PARTITION_REPORT">

src/pwh_lab/rh_video_display/bono_red_readme.txt

@@ -0,0 +1,61 @@
+The following files were generated for 'bono_red' in directory 
+/afs/athena.mit.edu/user/p/w/pwh/rh2/src/pwh_lab/rh_video_display:
+
+bono_red.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+bono_red.mif:
+   Memory Initialization File which is automatically generated by the
+   CORE Generator System for some modules when a simulation flow is
+   specified. A MIF data file is used to support HDL functional
+   simulation of modules which use arrays of values.
+
+bono_red.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+bono_red.sym:
+   Please see the core data sheet.
+
+bono_red.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+bono_red.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+bono_red.vhd:
+   VHDL wrapper file provided to support functional simulation. This
+   file contains simulation model customization data that is passed to
+   a parameterized simulation model for the core.
+
+bono_red.vho:
+   VHO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a VHDL design.
+
+bono_red.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+bono_red_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+bono_red_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+bono_red_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+bono_red_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+