A simple CPU consisting of 5 layer pipeline such as instruction fetch, instruction decode, execution, memory access, and write stage. Also added features such as forwarding, SRAM, and a cache system. The architecture is shown below:
A simple CPU consisting of 5 layer pipeline such as instruction fetch, instruction decode, execution, memory access, and write stage. Also added features such as forwarding, SRAM, and a cache system. The architecture is shown below: