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Computer architecture lab ARM processor with Verilog.

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.gitignore
.gitignore
 
 
ALU.v
ALU.v
 
 
ARM-Architecture.png
ARM-Architecture.png
 
 
ARM.mpf
ARM.mpf
 
 
ARM.v
ARM.v
 
 
Cache_Controller.v
Cache_Controller.v
 
 
Condition_Check.v
Condition_Check.v
 
 
Control_Unit.v
Control_Unit.v
 
 
EXE_Stage.v
EXE_Stage.v
 
 
EXE_Stage_Reg.v
EXE_Stage_Reg.v
 
 
Forwarding_Unit.v
Forwarding_Unit.v
 
 
Hazard_Detection_Unit.v
Hazard_Detection_Unit.v
 
 
ID_Stage.v
ID_Stage.v
 
 
ID_Stage_Reg.v
ID_Stage_Reg.v
 
 
IF_Stage.v
IF_Stage.v
 
 
IF_Stage_Reg.v
IF_Stage_Reg.v
 
 
Instruction_Memory.v
Instruction_Memory.v
 
 
MEM_Stage_Reg.v
MEM_Stage_Reg.v
 
 
Memory.v
Memory.v
 
 
PC_Reg.v
PC_Reg.v
 
 
README.md
README.md
 
 
Register_File.v
Register_File.v
 
 
SRAM.v
SRAM.v
 
 
SRAM_Controller.v
SRAM_Controller.v
 
 
Status_Register.v
Status_Register.v
 
 
TestBench.v
TestBench.v
 
 
Val2_Generator.v
Val2_Generator.v
 
 
WB_Stage.v
WB_Stage.v
 
 
tcl_stacktrace.txt
tcl_stacktrace.txt
 
 

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A simple CPU consisting of 5 layer pipeline such as instruction fetch, instruction decode, execution, memory access, and write stage. Also added features such as forwarding, SRAM, and a cache system. The architecture is shown below:

alt text

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Computer architecture lab ARM processor with Verilog.

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pipeline cache verilog sram

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