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[RTL872x] multiple SPI fixes #2768
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Tests to be done to make sure we don't run into regressions:
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So far the master passes everything but the slave fails. Commit 6334474
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I have repeatedly run the |
@eberseth Have you updated the system-part and test application for both SPI master and slave device? I just ran the whole test several times and all passed. |
The SPI master/slave fixture test always passed for me. I was using two Photon2(s) to run the test. |
I am running two Borons. I have updated the system parts on both. |
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I tested the spi_master_slave
wiring tests
- Photon 2 master SPI <--> Photon 2 slave SPI1
- All fail: I assume SPI1 slave mode on RTL platform is still broken?
- Photon 2 Master SPI <--> Boron slave SPI1
- All passed:
Test summary: 26 passed, 0 failed, and 0 skipped, out of 26 test(s).
- All passed:
- Argon master SPI <--> Photon 2 slave SPI1
- Mostly passed:
Assertion failed: (strncmp((const char *)SPI_Master_Rx_Buffer, "SPI Slave is doing good", sizeof("SPI Slave is doing good")) == 0=0) == (true=1), file tests/wiring/spi_master_s
lave/spi_master/spi_master.cpp, line 309.
Test 17_SPI_Master_Slave_Master_Variable_Length_Transfer_DMA_Synchronous_MODE1_LSB failed.
Assertion failed: (SPI_Master_Slave_Change_Mode(0x02, 1, transferFunc)=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.cpp, line 495.
Test 18_SPI_Master_Slave_Master_Variable_Length_Transfer_No_DMA_MODE2_MSB failed.
Assertion failed: (SPI_Master_Slave_Change_Mode(0x02, 1, transferFunc)=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.cpp, line 503.
Test 19_SPI_Master_Slave_Master_Variable_Length_Transfer_DMA_MODE2_MSB failed.
Assertion failed: (SPI_Master_Slave_Change_Mode(0x02, 1, transferFunc)=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.cpp, line 511.
Test 20_SPI_Master_Slave_Master_Variable_Length_Transfer_DMA_Synchronous_MODE2_MSB failed.
Assertion failed: (SPI_Master_Slave_Change_Mode(0x02, 0, transferFunc)=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.cpp, line 521.
Test 21_SPI_Master_Slave_Master_Variable_Length_Transfer_No_DMA_MODE2_LSB failed.
Assertion failed: (SPI_Master_Slave_Change_Mode(0x02, 0, transferFunc)=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.cpp, line 529.
Test 22_SPI_Master_Slave_Master_Variable_Length_Transfer_DMA_MODE2_LSB failed.
Assertion failed: (SPI_Master_Slave_Change_Mode(0x02, 0, transferFunc)=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.cpp, line 537.
Test 23_SPI_Master_Slave_Master_Variable_Length_Transfer_DMA_Synchronous_MODE2_LSB failed.
Test 24_SPI_Master_Slave_Master_Const_String_Transfer_DMA passed.
Assertion failed: (strncmp((const char *)SPI_Master_Rx_Buffer_Supper, txString, strlen(txString)) == 0=0) == (true=1), file tests/wiring/spi_master_slave/spi_master/spi_master.
cpp, line 598.
Test 25_SPI_Master_Slave_Master_Reception failed.
Test summary: 18 passed, 8 failed, and 0 skipped, out of 26 test(s).
I will review the DMA configuration / operation changes next. This looks like the most relevant changes in this PR
I read through the DMA operation and it seems to make sense to me. I think the biggest change here is the DCache invalidation steps with the tx/rx buffers.
I would have to debug the tests and HAL in depth to understand the above test failures since nothing is obviously wrong to me...
@scott-brust Have you updated the system-part that is built against the branch in this PR for Photon2 slave role as well? |
Yes, Ill double check it tomorrow. Should all the tests pass with P2 Master <-> P2 slave? Or just Gen3 Master <-> P2 slave? |
The fixture tests all passed with P2 Master <-> P2 slave on my side. |
I cant get them to consistently pass. I always get failures at some point in the test run. Things break after that. |
Problem
SPI.transfer(byte)
may lose dataSPI.begin()
won't applySPI.transfer(txBuf, nullptr, size, callback)
will lose data if CS pin is deasserted after the callback is invokedSteps to Test
user/tests/wiring/spi_master_slave
References
N/A
Completeness