Skip to content

Latest commit

 

History

History
470 lines (337 loc) · 30.9 KB

RELEASE_NOTES.md

File metadata and controls

470 lines (337 loc) · 30.9 KB
Raw

AWS EC2 FPGA HDK+SDK Release Notes

AWS EC2 F1 Platform Features:

  • 1-8 Xilinx UltraScale+ VU9P based FPGA slots
  • Per FPGA Slot, Interfaces available for Custom Logic(CL):
    • One x16 PCIe Gen 3 Interface
    • Four DDR4 RDIMM interfaces (with ECC)
    • AXI4 protocol support on all interfaces
  • User-defined clock frequency driving all CL to Shell interfaces
  • Multiple free running auxiliary clocks
  • PCI-E endpoint presentation to Custom Logic(CL)
    • Management PF (physical function)
    • Application PF
  • Virtual JTAG, Virtual LED, Virtual DIP Switches
  • PCI-E interface between Shell(SH) and Custom Logic(CL).
    • SH to CL inbound 512-bit AXI4 interface
    • CL to SH outbound 512-bit AXI4 interface * Multiple 32-bit AXI-Lite buses for register access, mapped to different PCIe BARs
    • Maximum payload size set by the Shell
    • Maximum read request size set by the Shell
    • AXI4 error handling * DDR interface between SH and CL
    • CL to SH 512-bit AXI4 interface
    • 1 DDR controller implemented in the SH (always available)
    • 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)

Release 1.4.4 (See ERRATA for unsupported features)

  • Fixed compile issues in simulation while using 3rd party simulators (synopsys VCS, Cadence IES and Mentor Questasim).

Release 1.4.3 (See ERRATA for unsupported features)

  • DRAM Data Retention - With DRAM data retention, developers can simply load a new AFI and continue using the data that is persistently kept in the DRAM attached to the FPGA, eliminating unnecessary data movements and greatly improving the overall application performance.
  • Virtual Ethernet - Provides a low latency network interface for EC2 F1, that enables high performance hardware acceleration to ethernet based applications on AWS like firewalls, routers and advanced security virtual appliances. With Virtual Ethernet, developers are able to create F1 accelerators that process ethernet packets directly from user-space on the FPGA with high throughput and low-latency.
  • Developer AMI v1.5 with Vivado/SDx 2018.2 tools - New FPGA developer AMI supporting Vivado 2018.2 for faster compile times, higher frequencies and improved timing closure

Release 1.4.2 (See ERRATA for unsupported features)

  • Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-862.3.3.el7.x86_64

Release 1.4.1 (See ERRATA for unsupported features)

  • Simulation performance Improvements
    • DDR Behavioural Model- Hardware simulations use an AXI memory model to run 4X faster by skipping DDR initialization. Please refer to this README on how to use this feature in your simulation.
    • DDR Backdoor Loading- Hardware simulation time is reduced by pre-loading data directly into memory models. Please refer to this README for example tests that demonstrate this feature.
  • Fixed Issues
    • XOCL Driver update to address synchronization issues.
    • Fixed XOCL driver issues when using ubuntu distribution for Linux OS.
    • Improved Performance for cl_dram_dma Public AFI.
    • SDAccel 3rd party examples updated to use Shell V1.4 DSA.
    • Fixed AFI Manifest generation in IPI flow.
    • HLX button fixed in IPI
    • FPGA Library update

Release 1.4.0 (See ERRATA for unsupported features)

  • New Shell Stable: v04261818. Starting with release v1.4.0, the AWS FPGA shell stable has been updated and only supports Xilinx 2017.4 SDx/Vivado. All previous versions of tools and shells are not supported with this developer kit shell release.

  • The previous shell (v071417d3) will be supported until 09/01/2018. Developers are required to use the developer kit v1.3.X branch for all shell version v071417d3 development.

  • Release 1.4.0 greatly improves the performance of the DMA (for interrupt driven DMA on the cl_dram_dma example design). This is accomplished through a combination of shell changes to relax DMA timeouts and a new XDMA software driver option. We have ported the relevant HDK examples to the XDMA driver in this release. EDMA is still supported, and developers can freely choose which DMA driver to use as part of their host application.

Supported Tools and Environment

  • The HDK and SDK are designed for Linux environment and has not been tested on other platforms
  • The First installation of AWS FPGA SDK requires having gcc installed on the instance. If it's not available, try sudo yum update && sudo yum group install "Development Tools"
  • The HDK build step requires having Xilinx's Vivado tool and Vivado License Management running. These are provided with AWS FPGA Developer AMI at no additional cost
  • This release is tested and validated with Xilinx 2017.4 SDx/Vivado
  • Developers that choose to develop on-premises need to have Xilinx license 'EF-VIVADO-SDX-VU9P-OP' installed. For more help, please refer to the on-premises licensing help
  • The following simulators are supported with this HDK: **Vivado XSIM RTL simulator ** MentorGraphic's Questa RTL simulator (with a separate license from MentorGraphics) ** Synopsys' VCS RTL simulator (with a separate license from Synopsys)

License Requirements

The HDK and SDK in the FPGA development kit have different licenses. For more details please refer to the HDK License and the SDK License.

FAQs

**Q: How do I know which HDK version I have on my instance/machine? **

Look for the ./hdk/hdk_version.txt file.

**Q: How do I know what my Shell version is? **

The Shell version of an FPGA slot is available through the FPGA Image Management tools. See the description of fpga-describe-local-image for more details on retrieving the shell version from a slot.

**Q: How do I know what version of FPGA Image management tools are running on my instance? **

The FPGA Image management tools version is reported with any command executed from these tools. See the description of fpga-describe-local-image for more details.

Q: How do I update my existing design with this release?

  1. Start by either cloning the entire GitHub structure for the HDK release or downloading new directories that have changed. AWS recommends an entire GitHub clone to ensure no files are missed
  2. Update the CL design to conform to the new AWS_Shell_Interface_Specification TODO: add link. TODO: need a doc to outline what changes are a MUST in this upgrade, and which ones are optional?
  3. Follow the process for AFI generation outlined in aws-fpga/hdk/cl/examples/readme.md
  4. Update FPGA Image Management Tools to the version included in aws-fpga/sdk/management TODO: SDaccel design have different steps?

Q: How do I get support?

The FPGA Development forum provides an easy access to Developer support. It's the first place to go to post questions, suggestions and receive important announcements from the AWS FPGA team. To gain access to the user forum, please go to https://forums.aws.amazon.com/index.jspa and login. To be notified of important messages you will need to click the “Watch Forum” button on the right side of the screen.

**Q: How do I know which HDK GitHub release I am working with? **

See the release notes at the top of the GitHub directory to identify the version of your GitHub clone.

TODO: The following major features are included in this HDK release:

Previous release notes

Release 1.3.X Details (See ERRATA for unsupported features)

The following major features are included in this HDK release:

1. New Shell, with modified Shell/CL interface. Changes are covered in:

  • The floorplan has been enhanced to enable more optimal CL designs through better timing closure and reduced congestion at the CL to Shell interface.
  • AWS_Shell_Interface_Specification.md has been updated. See cl_ports.vh for the updated port list
  • AWS Shell DCP is stored in S3 and fetched/verified when hdk_setup.sh script is sourced.

2. Integrated DMA

  • DMA functionality has been enhanced to allow DMA transactions of up to 1MB.
  • Multi-queue in each direction is now supported
  • The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
  • DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
  • A corresponding AWS Elastic DMA (EDMA) driver is provided.
  • EDMA Installation Readme provides installation and usage guidelines
  • See Kernel_Drivers_README for more information on restrictions for this release

3. PCI-M

  • The PCI-M interface is fully supported for CL generated transactions to the Shell.

4. URAM

  • Restrictions on URAM have been updated to enable 100% of the URAM with a CL to be utilized. See documentation on enabling URAM utilization: URAM_options

5. Vivado IP Integrator (IPI) and GUI Workflow

6. Build Flow improvments

7. VHDL

8. AXI Interface Checking

  • Protocol checks have been added to the CL-Shell interface to detect and report CL errors for enhanced CL debugging.
  • Transaction timeout values on the CL-Shell interface have been increased to allow for longer CL response times.
  • See Shell_Interface_Specification

9. Support for Vivado 2017.1 SDX Build

  • The FPGA Development AMI includes Vivado 2017.1 SDX
    • Get the 1.3.0+ AMI by selecting the version from the marketplace.
  • Older Vivado versions will not be supported

10. SDK changes

  • Synchronous (default) mode for fpga-load-local-image and fpga-clear-local-image. For example, in synchronous mode (default) fpga-load-local-image will wait for the AFI to transition to the "loaded" state, perform a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id, and display the final state for the given FPGA slot number. Asynchronous operation is preserved with the "-A" option to both fpga-load-local-image and fpga-clear-local-image.
  • The corresponding fpga_mgmt_load_local_image_sync and fpga_mgmt_clear_local_image_sync are provided by the fpga_mgmt library for use in C/C++ programs.

Release 1.3.7 (See ERRATA for unsupported features)

  • Support for Xilinx SDx/Vivado 2017.1 and Xilinx SDx/Vivado 2017.4 . The HDK and SDAccel setup scripts configure the development environment based on the tool version found in the PATH environment variable.
  • Dynamic Software Acceleration (OpenCL) platform – The AWS platform is dynamically configured during compile time to optimize unused DDR/Debug logic, free up FPGA resources and reduce compile times. Developers can instantiate up to 60 kernels (up from the max 16 2017.1 supported). See 2017.4 Migration Document and SDAccel User Guide
  • OpenCL Kernel profiling – During compile time, profiling logic can be automatically inserted to enable generation of kernel profile data. Profile data can be viewed using the SDx IDE under profile summary report and timeline trace report. See chapter 6 within the SDAccel Environment Profiling and Optimization Guide
  • OpenCL Hardware Emulation Debug – GDB-like debug allows developers a view of what is going on inside the kernel during hardware emulation. Debug capabilities include start/stop at intermediate points and memory inspection. See chapter 6 within the SDAccel Environment Profiling and Optimization Guide
  • Post-synthesis and place/route optimization is now supported in OpenCL development environment. New XOCC options: reuse_synth and reuse_impl
  • Customer simulation environment improvements and bug fixes:
    • 8 Additional tests that will help the developer with using the simulation environment and shell simulation model
    • Simulation model support for non DW aligned accesses
    • Co-simulation support
  • EDMA Driver fixes:
    • Prevent timeouts due to scanning of the BARs for DMA hardware
    • Driver compilation support for 4.14 Linux kernel
  • HDK improvements and fixes:
    • cl_dram_dma improvements to make enabling/disabling DDRs easier
    • encrypt.tcl now clears out old files
    • URAM example timing improvements
  • IPI Improvements:
    • HLS example
    • Script based approach for running the examples

Release 1.3.6 (See ERRATA for unsupported features)

  • Simulation model bug fix for transfer size of 64 bytes.
  • Xilinx 2017.1 Patch AR70350 - fixes report_power hangs. Patch is automatically applied during setup scripts using MYVIVADO environment variable.
  • Updated synthesis scripts with -sv option when calling read_verilog.
  • Added documentation on us-gov-west-1 (GovCloud US).
  • Minor EDMA driver fixes and improvements.

Release 1.3.5 (See ERRATA for unsupported features)

  • Amazon FPGA Images (AFIs) Tagging - To help with managing AFIs, you can optionally assign your own metadata to each AFI in the form of tags. Tags are managed using the AWS EC2 CLI commands create-tags, describe-tags and delete-tags. Tags are custom key/value pairs that can be used to identify or group EC2 resources, including AFIs. Tags can be used as filters in the describe-fpga-images API to search and filter the AFIs based on the tags you add.
  • EDMA driver fixes and improvements, including polled DMA descriptor completion mode which improves performance on smaller IO (<1MB).
  • AFI Power metrics and warnings – developers can avoid power violations by monitoring metrics that provide recent FPGA power, maximum FPGA power, and average FPGA power. CL designs can use power state pins to help developers throttle CL to avoid power violation.
  • Improved IPI 3rd party simulator support.
  • Simulation model fixes.
  • SDAccel improvements - Removal of settings64 script from SDAccel setup and switching between DSAs.

Release 1.3.4 (See ERRATA for unsupported features)

  • EDMA/XDMA Driver improvements
  • Additional SDAccel Platforms
    • 1DDR for faster build times and smaller expanded shell
    • RTL Kernel Debug adds support for virtual jtag debug on RTL kernels
  • IP Integrator GUI (HLx) improvements
    • CL_DRAM_DMA fixes and improvements
      • Dual master support
  • Simulation environment fixes and improvements
    • AXI/AXIL Protocol checkers
    • Shell model improvements
    • SW co-simulation support on cl_hello_world
    • DDR Model patch
  • Updated SH_DDR module in preparation for upcoming feature release

Release 1.3.3 (See ERRATA for unsupported features)

  • New FPGA Image APIs for deleting and reading/editing attributes

Release 1.3.2 (See ERRATA for unsupported features)

  • SDAccel general availability

Release 1.3.1 (See ERRATA for unsupported features)

  • EDMA Driver release 1.0.29 - MSI-X fixes
  • Improved IPI documentation
  • Documentation updates
  • Build flow fixes
  • Public LTX files for use with hdk examples AFIs

Release 1.3.0 (See ERRATA for unsupported features)

  • FPGA initiated read/write over PCI (PCI-M)
  • Redesigned Shell - improved the shell design to allow more complex place and route designs to meet timing
  • Expanded DMA support
  • Improved URAM utilization
  • Improved AXI Interface checking
  • New customer examples/workflows: IP Integrator, VHDL, and GUI
  • SDAccel preview is accepting developers - See README registration

Release 1.2.4

  • AWS SDK API aws ec2 describe-fpga-images released. See describe-fpga-images document for details on how to use this API. Requires Developer AMI 1.2.4 or awscli upgrade: pip install --upgrade --user awscli
  • Fix cl_dram_dam debug probes (.ltx) generation in build scripts
  • Fixed bugs with DMA in the simulation model and testbench

Release 1.2.3

  • New Errata
  • Added debug probes (.ltx) generation to build scripts
  • Fixed a bug with the simulation model that fixed the AXI behavior of wlast on unaligned address
  • Added timeout debug documentation

Release 1.2.2

  • Expanded clock recipes
  • Virtual JTAG documentation updates
  • Reduced DCP build times by 13% (34 mins) for cl_dram_dma example by adding an option to disable virtual jtag
  • Included encryption of .sv files for CL examples

Release 1.2.1

  • Updated CL example build scripts with Prohibit URAM sites
  • EDMA Performance improvements
  • Expanded EC2 Instance type support
  • CL Examples @250Mhz (Clock recipe A1)
  • Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG)

Release 1.2.0 Content Overview and New Features Details

1. New Shell, with modified Shell/CL interface. Changes are covered in:

  • New Shell Stable: 0x04151701: ./hdk/common/shell_v04151701
  • cl_ports.vh have the updated port list
  • AWS_Shell_Interface_Specification.md has been updated
  • Updated the xdc timing constrains under constraints to match the new interfaces
  • Updated CL HELLO WORLD example to use the new cl_ports.vh
  • DCP for the latest shell v04151701. AWS Shell DCP is stored in S3 and fetched/verified when hdk_setup.sh script is sourced.

2. Integrated DMA in Beta Release. AWS Shell now includes DMA capabilities on behalf of the CL

  • The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
  • DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
  • A corresponding AWS Elastic DMA (EDMA) driver is provided.
  • EDMA Installation Readme provides installation and usage guidelines
  • The initial release supports a single queue in each direction
  • DMA support is in Beta stage with a known issue for DMA READ transactions that cross 4K address boundaries. See Kernel_Drivers_README for more information on restrictions for this release

3. CL User-defined interrupt events. The CL can now request sending MSI-X to the instance CPU

4. Added a Mandatory Manifest.txt file submitted with each DCP via create-fpga-image API

  • File content defined in AFI Manifest
  • AFI_Manifest.txt is created automatically if the developer is using the aws_build_dcp_from_cl.sh script
  • PCI Vendor ID and Device ID are part of the manifest
  • Shell Version is part of the manifest
  • The Manifest.txt file is required for AFI generation
  • All the examples and documentation for build include the description and dependency on the Manifest.txt

5. Decoupling Shell/CL interface clocking from the internal Shell Clock

  • All the Shell/CL interfaces running off clk_main_a0, and no longer required to be 250Mhz.
  • The default frequency using the HDK build flow for clk_main_a0 is 125Mhz as specified in recipe number A0. Allowing CL designs to have flexible frequency and not be constrained to 250Mhz only. All CL designs must include the recipe number in the manifest.txt file in order to generate an AFI.
  • All xdc scripts have been updated to clk_main_a0 and to reference a table with the possible clocks’ frequencies combinations
  • Updated CL_HELLO_WORLD and CL_DRAM_DMA examples to use the clk_main_a0

6. Additional User-defined Auxiliary Clocks

Additional tunable auxiliary clocks are generated by the Shell and fed to the CL. The clocks frequencies are set by choosing a clock recipe per group from a set of predefined frequencies combination in clock recipes table

  • Clock frequency selection is set during build time and recorded in the manifest.txt (which should include the clock_recipe_a/b/c parameters)
  • Clock frequency programming in the FPGA slot itself occurs when the AFI is loaded. The list of supported frequencies is available here
  • See AWS_Shell_Interface_Specification for details on the clocking to the CL
  • See AFI Manifest for details on the AFI manifest data
  • xdc is automatically updated with the target frequency (WIP)

7. Additional PCIe BARs and update PCIe Physical Function mapping

** The AppPF now has 4 different PCIe BARs:**

  • BAR0 and BAR1 support 32-bit access for different memory ranges of the CL through separate AXI-L interfaces
  • BAR2 is used exclusively for the DMA inside the Shell and MSI-X interrupt tables
  • BAR4 expanded to 128GiB to cover all external DRAM memory space

** ManagementPF added additional PCIe BARs:**

** MgmtPF and AppPF are now represented as different PCIe devices in F1 instances:**

  • Each FPGA Slot will occupy two PCIe buses, one for AppPF and one for MgmtPF

8. Expanded AppPF BAR4 space to 128GiB

9. Added wider access on the Shell to CL AXI4 512-bit bus (sh_cl_dma_pcis)

  • Wider access provides higher bandwidth DMA and host to FPGA access
  • Instance CPU can now burst full 64-byte write burst to AppPF PCIe BAR4 if mapped as Burstable (a.k.a WC: WriteCombine) (WIP)
  • pci_poke_burst() and pci_poke64() calls were added to fpga_pci library to take advantage of this
  • CL_DRAM_DMA and CL_HELLO_WORLD examples support for a wider access was added

10. Support larger than 32-bit access to PCIe space

  • Large inbound transaction going to AppPF PCIe BAR4 will be passed onward to the CL
  • Large inbound transactions going to the other BARs will be split by the Shell to multiple 32-bit accesses, and satisfy AXI-L protocol specification.

11. Enhanced AXI4 error handling and reporting

  • Additional error conditions detected on the CL to Shell Interface and reported through fpga-describe-image tool
  • See AWS Shell Interface Specification for more details
  • FPGA Management Tool metrics output covers the additional error handling details

12. Expanded AXI ID space throughout the design

  • The AXI buses between Shell and CL support an expanded number of AXI ID bits to allow for bits to be added by AXI fabrics See AWS Shell Interface Specification for more details

13. Shell to CL interface metrics.

  • New metrics for monitoring the Shell to CL are available from the AFI Management Tools.
  • See fpga mgmt tools readme for more details

14. Virtual LED/DIP Switches.

  • Added CL capability to present virtual LEDs and push virtual DIP switches indications to the CL, set and read by FPGA Management Tools and without involving CL logic, providing the developer an environment similar to developing on local boards with LED and DIP switches
  • See new commands in FPGA Image Tools for description of the new functionality
  • CL_HELLO_WORLD example includes some logic to set LED and adjust according to vDIP
  • See AWS Shell Interface Specification for more details

15. Virtual JTAG

  • The Shell has the capability for supporting CL integrated Xilinx debug cores like Virtual I/O (VIO) and Integrated Logic Analyzer (ILA) and includes support for local/remote debug by running XVC
  • Virtual_JTAG_XVC describes how to use Virtual JTAG from Linux shell
  • cl_debug_bridge module was added to HDK common directory
  • Support for generating .ltx files after create-fpga-image was added. .ltx file is required when running interactive ILA/VIO debug (WIP)
  • Build tcl and xdc includes the required changes to enable Virtual JTAG
  • See CL_DRAM_DMA for examples on using Virtual JTAG and XVC for debug

16. Examples summary table

17. Updated CL_HELLO_WORLD Example

  • Matching the new Shell/CL interface
  • Add support for 32-bit peek/poke via ocl_ AXI-L bus
  • Virtual JTAG support with Xilinx ILA and VIO debug cores
  • Demonstrate the use of Virtual LED and Virtual DIPSwitch
  • Runtime software examples, leveraging fpga_pci and fpga_mgmt C-libraries
  • Updated PCIe Vendor ID and Device ID
  • See CL HELLO WORLD readme for more details

18. Added CL_DRAM_DMA Example

  • Mapping AppPF PCIe BAR4 to DRAM
  • Using DMA to access same DRAM
  • Using SystemVerilog Bus constructs to simplify the code
  • Demonstrate the use of User interrupts
  • Demonstrate the use of bar1_ AXI-L bus
  • Includes Runtime C-code application under CL_DRAM_DMA software
  • See CL_DRAM_DMA README

19. Software Programmer View document

20. Two C-libraries for FPGA PCIe access and for FPGA Management

  • The C-libraries are simplifying and adding more protections from developer’s mistakes when writing a runtime C-application
  • Fpga_mgmt.h cover the APIs for calling management functions
  • Fpga_pcie.h covers the API for access the various PCI memory spaces of the FPGA
  • CL_HELLO_WORLD and CL_DRAM_DMA examples updated to use these libraries.

21. VHDL support is added

  • Included Vivado encryption key file for VHDL
  • Added VHDL-specific line in encrypt.tcl reference files
  • Developer would need to add read_vhdl in create_dcp_from_cl.tcl

22. Additional FPGA Management Tools added

23. Support for Vivado 2017.1 Build

  • The FPGA Development AMI includes Vivado 2017.1
  • Older Vivado versions will not be supported

24. Embed the HDK version and Shell Version as part of the git tree

25. Initial Release of SDAccel and OpenCL Support (NA)

  • Updated documentation in /sdk/SDAccel (NA)
  • OpenCL runtime HAL for supporting SDAccel and OpenCL ICD in /sdk/userspace (NA)
  • SDAccel build post-processing to register SDAccel xcl.bin as AFI. (NA)

26. Simplify handling of unused Shell to CL interfaces

  • Developers can simply call `include "unused_BUS_NAME_template.inc" for every unused interface
  • List of potential files to include is available in $HDK_SHELL_DIR/design/interfaces/unused\*
  • cl_hello_world.sv and cl_dram_dma.sv provide examples (at the each of each file)

27. Support multiple Vivado versions

  • hdk_setup.sh compares between the list of Vivado versions supported by the HDK and the installed vivado versions
  • hdk_setup.sh would automatically choose the Vivado version from the available binaries in AWS FPGA Developer's AMI

28. Changes in DRAM controller setting to improve bandwidth utilization

  • Change address decoding to ROW_COL_INTLV mode
  • Enable auto precharge on COL A3