STM32 coding matrix

Pavel Revak edited this page Jun 27, 2018 · 10 revisions

STM32F051R8

F0 Architecture

Code Core Max freq FLASH SRAM PACKAGE
F0 CortexM0 48MHz 16KB - 256KB 4KB - 32KB 20 - 100 Mainstream
F1 CortexM3 72MHz 16KB - 1024KB 4KB - 96KB 36 - 144 Mainstream
F2 CortexM3 120MHz 128KB - 1024KB 64KB - 128KB 64 - 176 High performance
F3 CortexM4 72MHz 16KB - 512KB 16KB - 80KB 32 - 144 Mainstream
F4 CortexM4 180MHz 64KB - 2048KB 32KB - 384KB 36 - 216 High performance
F7 CortexM7 216MHz 512KB - 2048KB 320KB - 512KB 100 - 216 High performance
H7 CortexM7 400MHz 2048KB 1024KB 100 - 265 High performance
L0 CortexM0+ 32MHz 8KB - 192KB 2KB - 20KB 14 - 100 Ultra low-power
L1 CortexM3 32MHz 32KB - 512KB 4KB - 80KB 48 - 144 Ultra low-power
L4 CortexM4 80MHz 256KB - 1024KB 64KB - 128KB 32 - 144 Ultra low-power

R Pin count

Code Pin count Pin count Code
A 169 14 D
B 208 20 F
C 48 25 E
D 14 28 G
E 25 32 K
F 20 36 T
G 28 40 H
H 40 48 C
I 176 63 U
J 72 64 R
K 32 72 J
M 81 81 M
N 216 90 O
O 90 100 V
Q 132 132 Q
R 64 144 Z
T 36 169 A
U 63 176 I
V 100 208 B
Z 144 216 N
X 240 240 X

8 Flash size

Code Flash size
3 8KB
4 16KB
6 32KB
8 64KB
B 128KB
C 256KB
D 384KB
E 512KB
F 768KB
G 1024KB
I 2048KB
Z 192KB
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