fix: correct operand order for RISC-V R-type ops (#68)

perf-toolbox · Jun 16, 2024 · 7e40023 · 7e40023
1 parent 0220d03
commit 7e40023
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Showing 3 changed files with 21 additions and 21 deletions.
diff --git a/backends/riscv/checks/multi_sections.s b/backends/riscv/checks/multi_sections.s
@@ -17,15 +17,15 @@ main:
 # CHECK: module {
 # CHECK-NEXT: target.section ".text" {
 # CHECK-NEXT: ^example:
-# CHECK-NEXT: riscv.add rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sub rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sll rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.slt rs1 = t3, rs2 = t1, rd = t2, attrs = {}
+# CHECK-NEXT: riscv.add rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sub rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sll rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.slt rd = t3, rs1 = t1, rs2 = t2, attrs = {}
 # CHECK-NEXT: ^main:
-# CHECK-NEXT: riscv.sltu rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.srl rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sra rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.or rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.and rs1 = t3, rs2 = t1, rd = t2, attrs = {}
+# CHECK-NEXT: riscv.sltu rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.srl rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sra rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.or rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.and rd = t3, rs1 = t1, rs2 = t2, attrs = {}
 # CHECK-NEXT: }
 # CHECK-NEXT: }
diff --git a/backends/riscv/checks/simple.s b/backends/riscv/checks/simple.s
@@ -15,14 +15,14 @@ example:
 # CHECK: module {
 # CHECK-NEXT: target.section ".text" {
 # CHECK-NEXT: ^example:
-# CHECK-NEXT: riscv.add rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sub rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sll rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.slt rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sltu rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.srl rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.sra rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.or rs1 = t3, rs2 = t1, rd = t2, attrs = {}
-# CHECK-NEXT: riscv.and rs1 = t3, rs2 = t1, rd = t2, attrs = {}
+# CHECK-NEXT: riscv.add rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sub rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sll rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.slt rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sltu rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.srl rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.sra rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.or rd = t3, rs1 = t1, rs2 = t2, attrs = {}
+# CHECK-NEXT: riscv.and rd = t3, rs1 = t1, rs2 = t2, attrs = {}
 # CHECK-NEXT: }
 # CHECK-NEXT: }
diff --git a/backends/riscv/src/ops/alu.rs b/backends/riscv/src/ops/alu.rs
@@ -23,12 +23,12 @@ macro_rules! alu_op_base {
         #[derive(Op, OpAssembly, OpValidator)]
         #[operation(name = $op_name)]
         pub struct $struct_name {
+            #[operand]
+            rd: Register,
             #[operand]
             rs1: Register,
             #[operand]
             rs2: Register,
-            #[operand]
-            rd: Register,
             r#impl: OpImpl,
         }
     };
@@ -78,7 +78,7 @@ macro_rules! alu_ops {
                 let comma = one_of(|t| t == AsmToken::Comma).void();
 
                 let regs: Vec<Register> = preceded(opcode, separated(3, reg, comma)).parse_next(input)?;
-                let (rs1, rs2, rd) = (regs[0], regs[1], regs[2]);
+                let (rd, rs1, rs2) = (regs[0], regs[1], regs[2]);
 
                 let builder = input.get_builder();
                 let context = builder.get_context();