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Start of 68000 assembly book
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peter-mount committed Apr 27, 2022
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20 changes: 20 additions & 0 deletions content/asm/68000/_index.html
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---
type: "bookTitle"
title: "68000 Assembly Language"
linkTitle: "68000 Assembly"
weight: 20
categories:
- microprocessor
- book
book:
title: "68000 Microprocessor Family"
subTitle: "Notes about assembly language"
author: "Peter Mount, Area51.dev & Contributors"
copyright: "CC BY-SA"
---
<div class="printPageBreakAvoid">
<p>
This section covers assembly language for the 68000 Microprocessor family.
</p>
</div>

10 changes: 10 additions & 0 deletions content/asm/68000/opcodes/_index.html
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---
type: "manual"
title: "Opcodes"
linkTitle: "Instruction Set"
weight: 20
description: "Instruction Set"
---
<p>
In this section we cover every available instruction for the 68000 family of processors.
</p>
141 changes: 141 additions & 0 deletions content/asm/68000/opcodes/conventions/_index.html
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---
type: "manual"
title: "Conventions"
linkTitle: "Conventions"
weight: 1
description: "The conventions used in the documentation"
---

<div class="hexGrid">
<table>
<tbody>
<tr>
<th colspan="2">Operands</th>
</tr>
<tr>
<td>An</td>
<td>Any Address Register n (example: A3 is address register 3)</td>
</tr>
<tr>
<td>Dn</td>
<td>Any Data Register n (example: D5 is data register 5)</td>
</tr>
<tr>
<td>Rn</td>
<td>Any data or address registerData register D7–D0, used during compare.</td>
</tr>
<tr>
<td>PC</td>
<td>Program counter</td>
</tr>
<tr>
<td>SR</td>
<td>Status register</td>
</tr>
<tr>
<td>CCR</td>
<td>Condition codes register (low order byte of SR)</td>
</tr>
<tr>
<td>SSP</td>
<td>Supervisor stack pointer</td>
</tr>
<tr>
<td>USP</td>
<td>User stack pointer</td>
</tr>
<tr>
<td>SP</td>
<td>Active stack pointer (same as A7)</td>
</tr>
<tr>
<td>X</td>
<td>Extend flag of the CCR</td>
</tr>
<tr>
<td>N</td>
<td>Negative flag of the CCR</td>
</tr>
<tr>
<td>Z</td>
<td>Zero flag of the CCR</td>
</tr>
<tr>
<td>V</td>
<td>Overflow flag of the CCR</td>
</tr>
<tr>
<td>C</td>
<td>Carry flag of the CCR</td>
</tr>
<tr>
<td>Immediate data</td>
<td>Immediate data for the instruction</td>
</tr>
<tr>
<td>d</td>
<td>Address displacement</td>
</tr>
<tr>
<td>Source</td>
<td>Destination Source</td>
</tr>
<tr>
<td>contents</td>
<td>Destination contents</td>
</tr>
<tr>
<td>Vector</td>
<td>Location of exception vector</td>
</tr>
<tr>
<td>ea</td>
<td>Any valid effective address</td>
</tr>

<tr>
<th colspan="2">Notation</th>
</tr>
<tr>
<td>+</td>
<td>Arithmetic addition or postincrement indicator
</th></tr>
<tr>
<td>–</td>
<td>Arithmetic subtraction or predecrement indicator
</th></tr>
<tr>
<td>×</td>
<td>Arithmetic multiplication
</th></tr>
<tr>
<td>÷</td>
<td>Arithmetic division or conjunction symbol
</th></tr>
<tr>
<td>~</td>
<td>Invert; operand is logically complemented.
</th></tr>
<tr>
<td>Λ</td>
<td>Logical AND
</th></tr>
<tr>
<td>V</td>
<td>Logical OR
</th></tr>
<tr>
<td>⊕</td>
<td>Logical exclusive OR
</th></tr>
<tr>
<td>→</td>
<td>Source operand is moved to destination operand.
</th></tr>
<tr>
<td>←→</td>
<td>Two operands are exchanged.
</th></tr>
</tbody>
</table>
</div>
7 changes: 7 additions & 0 deletions content/asm/68000/opcodes/math/_index.html
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---
type: "manual"
title: "Arithmetic"
linkTitle: "Arithmetic"
weight: 3
description: Arithmetic operations
---
53 changes: 53 additions & 0 deletions content/asm/68000/opcodes/math/abcd/_index.html
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---
type: "manual"
title: "ABCD Add Decimal with Extend"
linkTitle: "ABCD"
#weight: 3
description: "ABCD Add Decimal with Extend"
tags:
- 68000 instruction
---
<table class="memoryMap4">
{{< m68k/block title="Operation" >}}
\(Source_{10} + Destination_{10} + X \longrightarrow Destination\)
{{< /m68k/block >}}

{{< m68k/block title="Syntax" >}}
ABCD Dy, Dx<br/>
ABCD -(Ay), -(Ax)
{{< /m68k/block >}}

{{< m68k/size byte="1" >}}

{{< m68k/block title="Description" >}}
<p>
Adds the source operand to the destination operand along with the extend bit,
and stores the result in the destination location. The addition is performed using binary-coded decimal arithmetic.
The operands, which are packed binary-coded decimal
numbers, can be addressed in two different ways:
</p>
<dl>
<dt>Data Register to Data Register</dt>
<dd>The operands are contained in the data registers specified in the instruction</dd>
<dt>Memory to Memory</dt>
<dd>
The operands are addressed with the predecrement addressing mode using the address registers specified in the
instruction.
</dd>
</dl>
<p>This operation is a byte operation only.</p>
{{< /m68k/block >}}

{{< m68k/flags
X="Set the same as the carry bit"
Z="Cleared if the result is nonzero; unchanged otherwise"
C="Set if a decimal carry was generated; cleared otherwise"
>}}
<div class="alert-info">
Normally, the Z condition code bit is set via programming before the start of an operation.
This allows successful tests for zero results upon completion of multiple-precision operations.
</div>
{{< /m68k/flags >}}

{{< m68k/instruction def="1100R10000Mr">}}
</table>
64 changes: 64 additions & 0 deletions content/asm/68000/opcodes/math/addx/_index.html
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---
type: "manual"
title: "ADDX"
linkTitle: "ADDX"
#weight: 3
description: "ADD Extended"
tags:
- 68000 instruction
m68k:
operation: "Source + Destination + X \\longrightarrow Destination"
asm:
- "ADDX Dy, Dx"
- "ADDX -(Ay), -(Ax)"
size:
- Byte
- Word
- Long
flags:
"x": "Set the same as the carry bit"
---
<table class="memoryMap4">
{{< m68k/block title="Operation" >}}
\(Source + Destination + X \longrightarrow Destination\)
{{< /m68k/block >}}

{{< m68k/block title="Syntax" >}}
ADDX Dy, Dx<br/>
ADDX -(Ay), -(Ax)<br/>
{{< /m68k/block >}}

{{< m68k/size byte="1" word="1" long="1" >}}

{{< m68k/block title="Description" >}}
<p>
Adds the source operand and the extend bit to the destination operand and
stores the result in the destination location. The operands can be addressed in two
different ways:
</p>
<dl>
<dt>Data register to data register</dt>
<dd>The data registers specified in the instruction contain the operands.</dd>
<dt>Memory to memory</dt>
<dd>The address registers specified in the instruction address the operands using the predecrement addressing mode.</dd>
</dl>
<p>
The size of the operation can be specified as byte, word, or long.
</p>
{{< /m68k/block >}}

{{< m68k/flags
X="Set the same as the carry bit"
N="Set if the result is negative; cleared otherwise"
Z="Cleared if the result is nonzero; unchanged otherwise"
V="Set if an overflow occurs; cleared otherwise"
C="Set if a carry is generated; cleared otherwise"
>}}
<div class="alert-info">
Normally, the Z condition code bit is set via programming before the start of an operation.
This allows successful tests for zero results upon completion of multiple-precision operations.
</div>
{{< /m68k/flags >}}

{{< m68k/instruction def="1101R1S00Mr">}}
</table>
8 changes: 8 additions & 0 deletions themes/area51/assets/scss/custom/table.scss
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}
}

td.font-normal {
font-size: 100% !important;
}

td.align-top {
vertical-align: top;
}

td:first-child,
td.blrtb,
td.blrt,
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4 changes: 4 additions & 0 deletions themes/area51/layouts/shortcodes/m68k/block.html
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<tr>
<th class="align-top">{{$.Get "title"}}:</th>
<td class="bnone text-left align-top font-normal">{{$.Inner}}</td>
</tr>
31 changes: 31 additions & 0 deletions themes/area51/layouts/shortcodes/m68k/flags.html
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<tr>
<th class="align-top">Flags:</th>
<td class="bnone text-left align-top font-normal">
<table class="memoryMap4">
<thead>
<tr>
<th>X</th>
<th>N</th>
<th>Z</th>
<th>V</th>
<th>C</th>
</tr>
</thead>
<tbody>
<tr>
<td class="brtb">{{- with $.Get "X"}}*{{else}}U{{end -}}</td>
<td class="brtb">{{- with $.Get "N"}}*{{else}}U{{end -}}</td>
<td class="brtb">{{- with $.Get "Z"}}*{{else}}U{{end -}}</td>
<td class="brtb">{{- with $.Get "V"}}*{{else}}U{{end -}}</td>
<td class="brtb">{{- with $.Get "C"}}*{{else}}U{{end -}}</td>
</tr>
</tbody>
</table>
<div>X {{with $.Get "X"}}{{.}}{{else}}Undefined{{end -}}</div>
<div>N {{with $.Get "N"}}{{.}}{{else}}Undefined{{end -}}</div>
<div>Z {{with $.Get "Z"}}{{.}}{{else}}Undefined{{end -}}</div>
<div>V {{with $.Get "V"}}{{.}}{{else}}Undefined{{end -}}</div>
<div>C {{with $.Get "C"}}{{.}}{{else}}Undefined{{end -}}</div>
{{.Inner}}
</td>
</tr>

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