introduce SVA checker

pezy-computing · Feb 16, 2024 · c27e013 · c27e013
1 parent 3c919d3
commit c27e013
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Showing 30 changed files with 712 additions and 280 deletions.
diff --git a/pzcorebus_1_to_m_switch/pzcorebus_1_to_m_switch.sv b/pzcorebus_1_to_m_switch/pzcorebus_1_to_m_switch.sv
@@ -29,7 +29,10 @@ module pzcorebus_1_to_m_switch
   parameter int                       DATA_DEPTH                    = 2,
   parameter int                       RESPONSE_DEPTH                = 2,
   parameter bit                       ALIGN_OUT                     = 0,
-  parameter int                       MINFO_WIDTH                   = get_request_info_width(BUS_CONFIG, 1)
+  parameter int                       MINFO_WIDTH                   = get_request_info_width(BUS_CONFIG, 1),
+  parameter bit                       SVA_CHECKER                   = 1,
+  parameter bit                       REQUEST_SVA_CHECKER           = SVA_CHECKER,
+  parameter bit                       RESPONSE_SVA_CHECKER          = SVA_CHECKER
 )(
   input   var                                 i_clk,
   input   var                                 i_rst_n,
@@ -60,23 +63,9 @@ module pzcorebus_1_to_m_switch
     );
   end
   else begin : g
-    pzcorebus_fifo #(
-      .BUS_CONFIG     (BUS_CONFIG     ),
-      .COMMAND_DEPTH  (COMMAND_DEPTH  ),
-      .COMMAND_VALID  (SLAVE_FIFO[0]  ),
-      .DATA_DEPTH     (DATA_DEPTH     ),
-      .DATA_VALID     (SLAVE_FIFO[0]  ),
-      .RESPONSE_DEPTH (RESPONSE_DEPTH ),
-      .RESPONSE_VALID (SLAVE_FIFO[1]  )
-    ) u_slave_fifo (
-      .i_clk          (i_clk      ),
-      .i_rst_n        (i_rst_n    ),
-      .i_clear        ('0         ),
-      .o_empty        (),
-      .o_almost_full  (),
-      .o_full         (),
-      .slave_if       (slave_if   ),
-      .master_if      (bus_if[0]  )
+    pzcorebus_connector u_connector (
+      .slave_if   (slave_if   ),
+      .master_if  (bus_if[0]  )
     );
   end
 
@@ -90,11 +79,12 @@ module pzcorebus_1_to_m_switch
     .ENABLE_BROADCAST             (ENABLE_BROADCAST             ),
     .ENABLE_BROADCAST_NON_POSTED  (ENABLE_BROADCAST_NON_POSTED  ),
     .WAIT_FOR_DATA                (WAIT_FOR_DATA                ),
-    .SLAVE_FIFO                   ('0                           ),
+    .SLAVE_FIFO                   (SLAVE_FIFO[0]                ),
     .MASTER_FIFO                  (MASTER_FIFO[0]               ),
     .COMMAND_DEPTH                (COMMAND_DEPTH                ),
     .DATA_DEPTH                   (DATA_DEPTH                   ),
-    .ALIGN_OUT                    (ALIGN_OUT                    )
+    .ALIGN_OUT                    (ALIGN_OUT                    ),
+    .SVA_CHECKER                  (REQUEST_SVA_CHECKER          )
   ) u_request_switch (
     .i_clk      (i_clk              ),
     .i_rst_n    (i_rst_n            ),
@@ -108,15 +98,16 @@ module pzcorebus_1_to_m_switch
   );
 
   pzcorebus_response_1_to_m_switch #(
-    .BUS_CONFIG     (BUS_CONFIG     ),
-    .MASTERS        (MASTERS        ),
-    .ENABLE_ARBITER (ENABLE_ARBITER ),
-    .PRIORITY_WIDTH (PRIORITY_WIDTH ),
-    .WEIGHT_WIDTH   (WEIGHT_WIDTH   ),
-    .WEIGHT         (WEIGHT         ),
-    .SLAVE_FIFO     ('0             ),
-    .MASTER_FIFO    (MASTER_FIFO[1] ),
-    .RESPONSE_DEPTH (RESPONSE_DEPTH )
+    .BUS_CONFIG         (BUS_CONFIG           ),
+    .MASTERS            (MASTERS              ),
+    .ENABLE_ARBITER     (ENABLE_ARBITER       ),
+    .PRIORITY_WIDTH     (PRIORITY_WIDTH       ),
+    .WEIGHT_WIDTH       (WEIGHT_WIDTH         ),
+    .WEIGHT             (WEIGHT               ),
+    .SLAVE_FIFO         (SLAVE_FIFO[1]        ),
+    .MASTER_FIFO        (MASTER_FIFO[1]       ),
+    .RESPONSE_DEPTH     (RESPONSE_DEPTH       ),
+    .SVA_CHECKER        (RESPONSE_SVA_CHECKER )
   ) u_response_switch (
     .i_clk            (i_clk              ),
     .i_rst_n          (i_rst_n            ),

diff --git a/pzcorebus_1_to_m_switch/pzcorebus_request_1_to_m_switch.sv b/pzcorebus_1_to_m_switch/pzcorebus_request_1_to_m_switch.sv
@@ -22,7 +22,8 @@ module pzcorebus_request_1_to_m_switch
   parameter int                 COMMAND_DEPTH               = 2,
   parameter int                 DATA_DEPTH                  = 2,
   parameter bit                 ALIGN_OUT                   = 0,
-  parameter int                 MINFO_WIDTH                 = get_request_info_width(BUS_CONFIG, 1)
+  parameter int                 MINFO_WIDTH                 = get_request_info_width(BUS_CONFIG, 1),
+  parameter bit                 SVA_CHECKER                 = 1
 )(
   input   var                                 i_clk,
   input   var                                 i_rst_n,
@@ -50,7 +51,8 @@ module pzcorebus_request_1_to_m_switch
       .THROUGH_NO_DATA_COMMAND  (1              ),
       .SLAVE_FIFO               (SLAVE_FIFO     ),
       .COMMAND_DEPTH            (COMMAND_DEPTH  ),
-      .DATA_DEPTH               (DATA_DEPTH     )
+      .DATA_DEPTH               (DATA_DEPTH     ),
+      .SVA_CHECKER              (SVA_CHECKER    )
     ) u_aligner (
       .i_clk        (i_clk      ),
       .i_rst_n      (i_rst_n    ),
@@ -70,7 +72,8 @@ module pzcorebus_request_1_to_m_switch
       .COMMAND_DEPTH  (COMMAND_DEPTH  ),
       .COMMAND_VALID  (SLAVE_FIFO     ),
       .DATA_DEPTH     (DATA_DEPTH     ),
-      .DATA_VALID     (SLAVE_FIFO     )
+      .DATA_VALID     (SLAVE_FIFO     ),
+      .SVA_CHECKER    (SVA_CHECKER    )
     ) u_fifo (
       .i_clk          (i_clk      ),
       .i_rst_n        (i_rst_n    ),
@@ -238,12 +241,13 @@ module pzcorebus_request_1_to_m_switch
 //--------------------------------------------------------------
   for (genvar i = 0;i < MASTERS;++i) begin : g_master_aligner
     if (is_memory_profile(BUS_CONFIG) && ALIGN_OUT && MASTER_FIFO) begin : g
-      pzcorebus_command_data_aligner #(
+      pzcorebus_command_data_aligner_core #(
         .BUS_CONFIG     (BUS_CONFIG     ),
         .RELAX_MODE     (1              ),
         .SLAVE_FIFO     (1              ),
         .COMMAND_DEPTH  (COMMAND_DEPTH  ),
-        .DATA_DEPTH     (DATA_DEPTH     )
+        .DATA_DEPTH     (DATA_DEPTH     ),
+        .SVA_CHECKER    (0              )
       ) u_aligner (
         .i_clk      (i_clk        ),
         .i_rst_n    (i_rst_n      ),
@@ -257,7 +261,8 @@ module pzcorebus_request_1_to_m_switch
         .COMMAND_DEPTH  (COMMAND_DEPTH  ),
         .COMMAND_VALID  (MASTER_FIFO    ),
         .DATA_DEPTH     (DATA_DEPTH     ),
-        .DATA_VALID     (MASTER_FIFO    )
+        .DATA_VALID     (MASTER_FIFO    ),
+        .SVA_CHECKER    (0              )
       ) u_fifo (
         .i_clk          (i_clk        ),
         .i_rst_n        (i_rst_n      ),

diff --git a/pzcorebus_1_to_m_switch/pzcorebus_response_1_to_m_switch.sv b/pzcorebus_1_to_m_switch/pzcorebus_response_1_to_m_switch.sv
@@ -17,7 +17,8 @@ module pzcorebus_response_1_to_m_switch
   parameter pzbcm_arbiter_weight_list WEIGHT          = '1,
   parameter bit                       SLAVE_FIFO      = 0,
   parameter bit                       MASTER_FIFO     = 0,
-  parameter int                       RESPONSE_DEPTH  = 2
+  parameter int                       RESPONSE_DEPTH  = 2,
+  parameter bit                       SVA_CHECKER     = 1
 )(
   input var                       i_clk,
   input var                       i_rst_n,
@@ -32,9 +33,10 @@ module pzcorebus_response_1_to_m_switch
 //  Slave FIFO
 //--------------------------------------------------------------
   pzcorebus_response_fifo #(
-    .BUS_CONFIG (BUS_CONFIG     ),
-    .DEPTH      (RESPONSE_DEPTH ),
-    .VALID      (SLAVE_FIFO     )
+    .BUS_CONFIG   (BUS_CONFIG     ),
+    .DEPTH        (RESPONSE_DEPTH ),
+    .VALID        (SLAVE_FIFO     ),
+    .SVA_CHECKER  (0              )
   ) u_slave_fifo (
     .i_clk          (i_clk    ),
     .i_rst_n        (i_rst_n  ),
@@ -95,9 +97,10 @@ module pzcorebus_response_1_to_m_switch
 //--------------------------------------------------------------
   for (genvar i = 0;i < MASTERS;++i) begin : g_master_fifo
     pzcorebus_response_fifo #(
-      .BUS_CONFIG (BUS_CONFIG     ),
-      .DEPTH      (RESPONSE_DEPTH ),
-      .VALID      (MASTER_FIFO    )
+      .BUS_CONFIG   (BUS_CONFIG     ),
+      .DEPTH        (RESPONSE_DEPTH ),
+      .VALID        (MASTER_FIFO    ),
+      .SVA_CHECKER  (SVA_CHECKER    )
     ) u_master_fifo (
       .i_clk          (i_clk        ),
       .i_rst_n        (i_rst_n      ),

diff --git a/pzcorebus_async_fifo/pzcorebus_async_fifo.sv b/pzcorebus_async_fifo/pzcorebus_async_fifo.sv
@@ -8,13 +8,16 @@ module pzcorebus_async_fifo
   import  pzcorebus_pkg::*,
           pzbcm_async_fifo_pkg::calc_default_depth;
 #(
-  parameter pzcorebus_config  BUS_CONFIG        = '0,
-  parameter int               STAGES            = `PZBCM_SYNCHRONIZER_DEFAULT_STAGES,
-  parameter int               COMMAND_DEPTH     = calc_default_depth(STAGES),
-  parameter int               DATA_DEPTH        = calc_default_depth(STAGES),
-  parameter int               RESPONSE_DEPTH    = calc_default_depth(STAGES),
-  parameter bit               MERGE_RESET       = '0,
-  parameter int               RESET_SYNC_STAGES = 2
+  parameter pzcorebus_config  BUS_CONFIG            = '0,
+  parameter int               STAGES                = `PZBCM_SYNCHRONIZER_DEFAULT_STAGES,
+  parameter int               COMMAND_DEPTH         = calc_default_depth(STAGES),
+  parameter int               DATA_DEPTH            = calc_default_depth(STAGES),
+  parameter int               RESPONSE_DEPTH        = calc_default_depth(STAGES),
+  parameter bit               MERGE_RESET           = '0,
+  parameter int               RESET_SYNC_STAGES     = 2,
+  parameter bit               SVA_CHECKER           = 1,
+  parameter bit               REQUEST_SVA_CHECKER   = SVA_CHECKER,
+  parameter bit               RESPONSE_SVA_CHECKER  = SVA_CHECKER
 )(
   input var           i_slave_clk,
   input var           i_slave_rst_n,
@@ -149,4 +152,27 @@ module pzcorebus_async_fifo
       .od_data        (slave_sresp            )
     );
   end
+
+//--------------------------------------------------------------
+//  SVA checker
+//--------------------------------------------------------------
+  if (PZCOREBUS_ENABLE_SVA_CHECKER) begin : g_sva
+    pzcorebus_request_sva_checker #(
+      .BUS_CONFIG   (BUS_CONFIG           ),
+      .SVA_CHECKER  (REQUEST_SVA_CHECKER  )
+    ) u_request_sva_checker (
+      .i_clk    (i_slave_clk    ),
+      .i_rst_n  (i_slave_rst_n  ),
+      .bus_if   (slave_if       )
+    );
+
+    pzcorebus_response_sva_checker #(
+      .BUS_CONFIG   (BUS_CONFIG           ),
+      .SVA_CHECKER  (RESPONSE_SVA_CHECKER )
+    ) u_response_sva_checker (
+      .i_clk    (i_master_clk   ),
+      .i_rst_n  (i_master_rst_n ),
+      .bus_if   (master_if      )
+    );
+  end
 endmodule
diff --git a/pzcorebus_async_fifo/pzcorebus_request_async_fifo.sv b/pzcorebus_async_fifo/pzcorebus_request_async_fifo.sv
@@ -13,7 +13,8 @@ module pzcorebus_request_async_fifo
   parameter int               COMMAND_DEPTH     = calc_default_depth(STAGES),
   parameter int               DATA_DEPTH        = calc_default_depth(STAGES),
   parameter bit               MERGE_RESET       = '0,
-  parameter int               RESET_SYNC_STAGES = 2
+  parameter int               RESET_SYNC_STAGES = 2,
+  parameter bit               SVA_CHECKER       = 1
 )(
   input var                 i_slave_clk,
   input var                 i_slave_rst_n,
@@ -113,4 +114,18 @@ module pzcorebus_request_async_fifo
       master_mdata  = '0;
     end
   end
+
+//--------------------------------------------------------------
+//  SVA checker
+//--------------------------------------------------------------
+  if (PZCOREBUS_ENABLE_SVA_CHECKER) begin : g_sva
+    pzcorebus_request_sva_checker #(
+      .BUS_CONFIG   (BUS_CONFIG   ),
+      .SVA_CHECKER  (SVA_CHECKER  )
+    ) u_sva_checker (
+      .i_clk    (i_slave_clk    ),
+      .i_rst_n  (i_slave_rst_n  ),
+      .bus_if   (slave_if       )
+    );
+  end
 endmodule
diff --git a/pzcorebus_async_fifo/pzcorebus_response_async_fifo.sv b/pzcorebus_async_fifo/pzcorebus_response_async_fifo.sv
@@ -12,7 +12,8 @@ module pzcorebus_response_async_fifo
   parameter int               STAGES            = `PZBCM_SYNCHRONIZER_DEFAULT_STAGES,
   parameter int               RESPONSE_DEPTH    = calc_default_depth(STAGES),
   parameter bit               MERGE_RESET       = '0,
-  parameter int               RESET_SYNC_STAGES = 2
+  parameter int               RESET_SYNC_STAGES = 2,
+  parameter bit               SVA_CHECKER       = 1
 )(
   input var                 i_slave_clk,
   input var                 i_slave_rst_n,
@@ -58,4 +59,18 @@ module pzcorebus_response_async_fifo
     .id_pop         (slave_if.mresp_accept  ),
     .od_data        (slave_sresp            )
   );
+
+//--------------------------------------------------------------
+//  SVA checker
+//--------------------------------------------------------------
+  if (PZCOREBUS_ENABLE_SVA_CHECKER) begin : g_sva
+    pzcorebus_response_sva_checker #(
+      .BUS_CONFIG   (BUS_CONFIG   ),
+      .SVA_CHECKER  (SVA_CHECKER  )
+    ) u_sva_checker (
+      .i_clk    (i_master_clk   ),
+      .i_rst_n  (i_master_rst_n ),
+      .bus_if   (master_if      )
+    );
+  end
 endmodule
diff --git a/pzcorebus_axi_bridge/pzcorebus_axi2corebus_simple_bridge.sv b/pzcorebus_axi_bridge/pzcorebus_axi2corebus_simple_bridge.sv
@@ -15,7 +15,10 @@ module pzcorebus_axi2corebus_simple_bridge
   parameter int               WRITE_DATA_FIFO_DEPTH = 2,
   parameter int               RESPONSE_FIFO_DEPTH   = 0,
   parameter int               BID_FIFO_DEPTH        = 8,
-  parameter bit               SUPPORT_4BYTES_ACCESS = 0
+  parameter bit               SUPPORT_4BYTES_ACCESS = 0,
+  parameter bit               SVA_CHECKER           = 1,
+  parameter bit               REQUEST_SVA_CHECKER   = SVA_CHECKER,
+  parameter bit               RESPONSE_SVA_CHECKER  = SVA_CHECKER
 )(
   input var           i_clk,
   input var           i_rst_n,
@@ -120,10 +123,12 @@ module pzcorebus_axi2corebus_simple_bridge
   end
 
   pzcorebus_fifo #(
-    .BUS_CONFIG     (COREBUS_CONFIG       ),
-    .COMMAND_DEPTH  (COMMAND_FIFO_DEPTH   ),
-    .DATA_DEPTH     (0                    ),
-    .RESPONSE_DEPTH (RESPONSE_FIFO_DEPTH  )
+    .BUS_CONFIG           (COREBUS_CONFIG       ),
+    .COMMAND_DEPTH        (COMMAND_FIFO_DEPTH   ),
+    .DATA_DEPTH           (0                    ),
+    .RESPONSE_DEPTH       (RESPONSE_FIFO_DEPTH  ),
+    .REQUEST_SVA_CHECKER  (REQUEST_SVA_CHECKER  ),
+    .RESPONSE_SVA_CHECKER (0                    )
   ) u_read_fifo (
     .i_clk          (i_clk        ),
     .i_rst_n        (i_rst_n      ),
@@ -216,10 +221,12 @@ module pzcorebus_axi2corebus_simple_bridge
   end
 
   pzcorebus_fifo #(
-    .BUS_CONFIG     (COREBUS_CONFIG         ),
-    .COMMAND_DEPTH  (COMMAND_FIFO_DEPTH     ),
-    .DATA_DEPTH     (WRITE_DATA_FIFO_DEPTH  ),
-    .RESPONSE_DEPTH (0                      )
+    .BUS_CONFIG           (COREBUS_CONFIG         ),
+    .COMMAND_DEPTH        (COMMAND_FIFO_DEPTH     ),
+    .DATA_DEPTH           (WRITE_DATA_FIFO_DEPTH  ),
+    .RESPONSE_DEPTH       (0                      ),
+    .REQUEST_SVA_CHECKER  (REQUEST_SVA_CHECKER    ),
+    .RESPONSE_SVA_CHECKER (0                      )
   ) u_write_fifo (
     .i_clk          (i_clk        ),
     .i_rst_n        (i_rst_n      ),
@@ -235,10 +242,12 @@ module pzcorebus_axi2corebus_simple_bridge
 //  Switch
 //--------------------------------------------------------------
   pzcorebus_m_to_1_switch #(
-    .BUS_CONFIG       (COREBUS_CONFIG ),
-    .SLAVES           (2              ),
-    .EXTERNAL_DECODE  (1              ),
-    .ENABLE_ARBITER   (2'b01          )
+    .BUS_CONFIG           (COREBUS_CONFIG       ),
+    .SLAVES               (2                    ),
+    .EXTERNAL_DECODE      (1                    ),
+    .ENABLE_ARBITER       (2'b01                ),
+    .REQUEST_SVA_CHECKER  (0                    ),
+    .RESPONSE_SVA_CHECKER (RESPONSE_SVA_CHECKER )
   ) u_switch (
     .i_clk            (i_clk                            ),
     .i_rst_n          (i_rst_n                          ),

diff --git a/pzcorebus_axi_bridge/pzcorebus_corebus2axi_simple_bridge.sv b/pzcorebus_axi_bridge/pzcorebus_corebus2axi_simple_bridge.sv
@@ -8,9 +8,12 @@ module pzcorebus_corebus2axi_simple_bridge
   import  pzcorebus_pkg::*,
           pzaxi_pkg::*;
 #(
-  parameter pzcorebus_config  COREBUS_CONFIG      = '0,
-  parameter pzaxi_config      AXI_CONFIG          = '0,
-  parameter int               MAX_WRITE_REQUESTS  = (2**16) - 1
+  parameter pzcorebus_config  COREBUS_CONFIG        = '0,
+  parameter pzaxi_config      AXI_CONFIG            = '0,
+  parameter int               MAX_WRITE_REQUESTS    = (2**16) - 1,
+  parameter bit               SVA_CHECKER           = 1,
+  parameter bit               REQUEST_SVA_CHECKER   = SVA_CHECKER,
+  parameter bit               RESPONSE_SVA_CHECKER  = SVA_CHECKER
 )(
   input var                   i_clk,
   input var                   i_rst_n,
@@ -185,4 +188,27 @@ module pzcorebus_corebus2axi_simple_bridge
     corebus_if.sresp_uniten = '1;
     corebus_if.sresp_last   = (axi_if.rlast) ? '1 : '0;
   end
+
+//--------------------------------------------------------------
+//  SVA checker
+//--------------------------------------------------------------
+  if (PZCOREBUS_ENABLE_SVA_CHECKER) begin : g_sva
+    pzcorebus_request_sva_checker #(
+      .BUS_CONFIG   (COREBUS_CONFIG       ),
+      .SVA_CHECKER  (REQUEST_SVA_CHECKER  )
+    ) u_request_sva_checker (
+      .i_clk    (i_clk      ),
+      .i_rst_n  (i_rst_n    ),
+      .bus_if   (corebus_if )
+    );
+
+    pzcorebus_response_sva_checker #(
+      .BUS_CONFIG   (COREBUS_CONFIG       ),
+      .SVA_CHECKER  (RESPONSE_SVA_CHECKER )
+    ) u_response_sva_checker (
+      .i_clk    (i_clk      ),
+      .i_rst_n  (i_rst_n    ),
+      .bus_if   (corebus_if )
+    );
+  end
 endmodule