Add basic filename/lineno to verilog backend

magma/backend/verilog.py

@@ -12,6 +12,15 @@
 from ..bits import SIntType
 from ..circuit import *
 from ..clock import wiredefaultclock
+import os
+
+def get_codegen_debug_info():
+    return os.environ.get('MAGMA_CODEGEN_DEBUG_INFO', False)
+
+def make_relative(path):
+    cwd = os.getcwd()
+    common_prefix = os.path.commonprefix([cwd, path])
+    return os.path.relpath(path, common_prefix)
 
 coreir_primitives_file_path = os.path.join(
     os.path.dirname(os.path.realpath(__file__)), "coreir_prims.v")
@@ -163,7 +172,10 @@ def compiledefinition(cls):
             # emit the structured verilog for each instance
             for instance in cls.instances:
                 wiredefaultclock(cls, instance)
-                s += compileinstance(instance) + ';\n'
+                s += compileinstance(instance) + ";"
+                if instance.filename and instance.lineno and get_codegen_debug_info():
+                    s += f" // Instanced at {make_relative(instance.filename)}:{instance.lineno}"
+                s +=  '\n'
 
             # assign to module output arguments
             for port in cls.interface.ports.values():
@@ -172,7 +184,10 @@ def compiledefinition(cls):
                     if output:
                         iname = vname(port)
                         oname = vname(output)
-                        s += 'assign %s = %s;\n' % (iname, oname)
+                        s += 'assign %s = %s;' % (iname, oname)
+                        if hasattr(port, "debug_info") and get_codegen_debug_info():
+                            s += f"  // Wired at {make_relative(port.debug_info[0])}:{port.debug_info[1]}"
+                        s += '\n'
 
         s += "endmodule\n"
 

tests/test_circuit/gold/test_simple_def.v

@@ -0,0 +1,6 @@
+module main (input [1:0] I, output  O);
+wire  inst0_O;
+And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O)); // Instanced at tests/test_circuit/test_define.py:13
+assign O = inst0_O;  // Wired at tests/test_circuit/test_define.py:17
+endmodule
+

tests/test_circuit/test_define.py

@@ -0,0 +1,24 @@
+import os
+import magma as m
+from magma.testing import check_files_equal
+
+
+def test_simple_def():
+    os.environ["MAGMA_CODEGEN_DEBUG_INFO"] = "1"
+    And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit),
+                            "O", m.Out(m.Bit))
+
+    main = m.DefineCircuit("main", "I", m.In(m.Bits(2)), "O", m.Out(m.Bit))
+
+    and2 = And2()
+
+    m.wire(main.I[0], and2.I0)
+    m.wire(main.I[1], and2.I1)
+    m.wire(and2.O, main.O)
+
+    m.EndCircuit()
+
+    m.compile("build/test_simple_def", main)
+    del os.environ["MAGMA_CODEGEN_DEBUG_INFO"]
+    assert check_files_equal(__file__, f"build/test_simple_def.v",
+                             f"gold/test_simple_def.v")