Change default compile target to coreir-verilog

magma/compile.py

@@ -19,28 +19,6 @@ def write_file(file_name, extension, code):
         file.write(code)
 
 
-class CheckAnyMantleCircuits(DefinitionPass):
-    def __init__(self, main):
-        super().__init__(main)
-        self.has_mantle_circuit = False
-
-    def __call__(self, definition):
-        if getattr(definition, "debug_info", False) and \
-                definition.debug_info.module.__name__.split(".")[0] == "mantle":
-            self.has_mantle_circuit = True
-
-    def _run(self, definition):
-        for instance in getattr(definition, "instances", []):
-            instancedefinition = type(instance)
-            self._run( instancedefinition )
-
-        self(definition)
-
-    def run(self):
-        super().run()
-        return self.has_mantle_circuit
-
-
 def __compile_to_coreir(main, file_name, opts):
     # Underscore so our coreir module doesn't conflict with coreir bindings
     # package.
@@ -84,21 +62,9 @@ def __compile_to_coreir(main, file_name, opts):
             "Running coreir failed"
 
 
-def compile(basename, main, output='verilog', **kwargs):
+def compile(basename, main, output='coreir-verilog', **kwargs):
     opts = kwargs.copy()
 
-    # If the output is verilog and the main circuit includes a mantle circuit
-    # and we're using the coreir mantle target, use coreir to generate verilog
-    # by setting the output to coreir-verilog
-    has_mantle_circuit = CheckAnyMantleCircuits(main).run()
-    if output == "verilog" and m.mantle_target == "coreir" and has_mantle_circuit:
-        warning("`m.compile` called with `output == verilog` and"
-                " `m.mantle_target == \"coreir\"` and mantle has been imported,"
-                " When generating verilog from circuits from the \"coreir\""
-                " mantle target, you should set `output=\"coreir-verilog\"`."
-                " Doing this automatically.")
-        output = 'coreir-verilog'
-
     # Rather than having separate logic for 'coreir-verilog' mode, we defer to
     # 'coreir' mode with the 'output_verilog' option set to True.
     if output == 'coreir-verilog':

tests/test_circuit/test_define.py

@@ -123,7 +123,7 @@ def test_unwired_ports_warnings(caplog):
 
     m.EndCircuit()
 
-    m.compile("build/test_unwired_output", main)
+    m.compile("build/test_unwired_output", main, "verilog")
     assert check_files_equal(__file__, f"build/test_unwired_output.v",
                              f"gold/test_unwired_output.v")
     assert caplog.records[-2].msg == "main.And2_inst0.I0 not connected"
@@ -144,7 +144,7 @@ def test_2d_array_error(caplog):
     m.EndCircuit()
 
     try:
-        m.compile("build/test_unwired_output", main)
+        m.compile("build/test_unwired_output", main, output="verilog")
         assert False, "Should raise exception"
     except Exception as e:
         assert str(e) == "Argument main.I of type Array[2, Array[3, Out(Bit)]] is not supported, the verilog backend only supports simple 1-d array of bits of the form Array(N, Bit)"  # noqa

tests/test_io/test_inout1.py

@@ -7,5 +7,5 @@ def test():
 
     wire(main.I, main.O)
 
-    compile("build/inout1", main)
+    compile("build/inout1", main, output="verilog")
     assert check_files_equal(__file__, "build/inout1.v", "gold/inout1.v")

tests/test_io/test_out1.py

@@ -7,5 +7,5 @@ def test():
 
     wire(1, main.O)
 
-    compile("build/out1", main)
+    compile("build/out1", main, output="verilog")
     assert check_files_equal(__file__, "build/out1.v", "gold/out1.v")

tests/test_io/test_out2.py

@@ -7,5 +7,5 @@ def test():
 
     wire(array([0,1]), main.O)
 
-    compile("build/out2", main)
+    compile("build/out2", main, output="verilog")
     assert check_files_equal(__file__, "build/out2.v", "gold/out2.v")

tests/test_ir/test_declaretest.py

@@ -11,5 +11,5 @@ def test():
     wire(inst0.O, main.O)
     EndCircuit()
 
-    compile("build/declaretest", main)
+    compile("build/declaretest", main, output="verilog")
     assert check_files_equal(__file__, "build/declaretest.v", "gold/declaretest.v")

tests/test_meta/test_class.py

@@ -23,5 +23,5 @@ def __call__(self, I):
 
     O( and2(I) )
 
-    compile("build/class", main)
+    compile("build/class", main, output="verilog")
     assert check_files_equal(__file__, "build/class.v", "gold/class.v")

tests/test_meta/test_creg.py

@@ -40,6 +40,6 @@ def definition(reg):
     print('wire O')
     wire(reg.O, O)
 
-    compile("build/creg", main)
+    compile("build/creg", main, output="verilog")
     assert check_files_equal(__file__, "build/creg.v", "gold/creg.v")
 

tests/test_verilog/test_from_file.py

@@ -21,7 +21,7 @@ def check_rxmod(RXMOD):
     check_port(RXMOD, "data", m.ArrayType, "output")
     check_port(RXMOD, "valid", m.BitType, "output")
 
-    m.compile("build/test_rxmod", RXMOD)
+    m.compile("build/test_rxmod", RXMOD, output="verilog")
     assert m.testing.check_files_equal(__file__, "build/test_rxmod.v",
             "gold/test_rxmod.v")
 
@@ -83,7 +83,7 @@ def test_from_sv():
 
     if os.path.exists("build/test_pe.sv"):
        os.remove("build/test_pe.sv")
-    m.compile("build/test_pe", test_pe)
+    m.compile("build/test_pe", test_pe, output="verilog")
 
     # Remove last line from generated file since magma adds an extra newline
     with open("tests/test_verilog/build/test_pe.sv", 'r') as f:

tests/test_wire/test_arg.py

@@ -10,7 +10,7 @@ def test_arg1():
     wire(main.I, buf.I)
     wire(buf.O, main.O)
 
-    compile("build/arg1", main)
+    compile("build/arg1", main, output="verilog")
     assert check_files_equal(__file__, "build/arg1.v", "gold/arg1.v")
 
 
@@ -25,7 +25,7 @@ def test_arg2():
     wire( main.I[1], a.I1 )
     wire(a.O, main.O)
 
-    compile("build/arg2", main)
+    compile("build/arg2", main, output="verilog")
     assert check_files_equal(__file__, "build/arg2.v", "gold/arg2.v")
 
 def test_pos():
@@ -37,7 +37,7 @@ def test_pos():
     wire(main.I, buf[0])
     wire(buf[1], main.O)
 
-    compile("build/pos", main)
+    compile("build/pos", main, output="verilog")
     assert check_files_equal(__file__, "build/pos.v", "gold/pos.v")
 
 def test_arg_array1():
@@ -55,7 +55,7 @@ def AndN(n):
     wire(array([0,1]), a.I)
     wire(a.O, main.O)
 
-    compile("build/array1", main)
+    compile("build/array1", main, output="verilog")
     assert check_files_equal(__file__, "build/array1.v", "gold/array1.v")
 
 
@@ -74,7 +74,7 @@ def AndN(n):
     wire(array([main.I, 1]), a.I)
     wire(a.O, main.O)
 
-    compile("build/array2", main)
+    compile("build/array2", main, output="verilog")
     assert check_files_equal(__file__, "build/array2.v", "gold/array2.v")
 
 
@@ -93,5 +93,5 @@ def AndN(n):
     wire(main.I, a.I)
     wire(a.O, main.O)
 
-    compile("build/array3", main)
+    compile("build/array3", main, output="verilog")
     assert check_files_equal(__file__, "build/array3.v", "gold/array3.v")

tests/test_wire/test_call.py

@@ -12,7 +12,7 @@ def test_call1():
     a( main.I0, main.I1 )
     wire(a, main.O)
 
-    compile("build/call1", main)
+    compile("build/call1", main, output="verilog")
     assert check_files_equal(__file__, "build/call1.v", "gold/call1.v")
 
 
@@ -31,5 +31,5 @@ def AndN(n):
     a( main.I )
     wire(a, main.O)
 
-    compile("build/call2", main)
+    compile("build/call2", main, output="verilog")
     assert check_files_equal(__file__, "build/call2.v", "gold/call2.v")

tests/test_wire/test_compose.py

@@ -14,6 +14,6 @@ def test():
     buf2(buf1)
     wire(buf2, main.O)
 
-    compile("build/compose", main)
+    compile("build/compose", main, output="verilog")
     assert check_files_equal(__file__, "build/compose.v", "gold/compose.v")
 

tests/test_wire/test_const.py

@@ -13,7 +13,7 @@ def test_const0():
     wire(0, buf.I)
     wire(buf.O, main.O)
 
-    compile("build/const0", main)
+    compile("build/const0", main, output="verilog")
     assert check_files_equal(__file__, "build/const0.v", "gold/const0.v")
 
 
@@ -27,7 +27,7 @@ def test_const1():
     wire(1, buf.I)
     wire(buf.O, main.O)
 
-    compile("build/const1", main)
+    compile("build/const1", main, output="verilog")
     assert check_files_equal(__file__, "build/const1.v", "gold/const1.v")
 
 
@@ -45,6 +45,6 @@ def test_const_bits(T, N):
     wire(1, buf.I)
     wire(buf.O, main.O)
 
-    compile(f"build/const_bits_{T.__name__}_{N}", main)
+    compile(f"build/const_bits_{T.__name__}_{N}", main, output="verilog")
     assert check_files_equal(__file__, f"build/const_bits_{T.__name__}_{N}.v",
                              f"gold/const_bits_{T.__name__}_{N}.v")

tests/test_wire/test_flip.py

@@ -12,5 +12,5 @@ def test_flip():
     wire(buf.I, bit(1))
     wire(main.O, buf.O)
 
-    compile("build/flip", main)
+    compile("build/flip", main, output="verilog")
     assert check_files_equal(__file__, "build/flip.v", "gold/flip.v")

tests/test_wire/test_named.py

@@ -11,7 +11,7 @@ def test_named1():
     buf(I=main.I)
     wire(buf.O, main.O)
 
-    compile("build/named1", main)
+    compile("build/named1", main, output="verilog")
     assert check_files_equal(__file__, "build/named1.v", "gold/named1.v")
 
 def test_named2():
@@ -24,7 +24,7 @@ def test_named2():
     a(I0=main.I[0], I1=main.I[1])
     wire(a.O, main.O)
 
-    compile("build/named2a", main)
+    compile("build/named2a", main, output="verilog")
     assert check_files_equal(__file__, "build/named2a.v", "gold/named2a.v")
 
 def test_named3():
@@ -38,7 +38,7 @@ def test_named3():
     a(I1=main.I[1])
     wire(a.O, main.O)
 
-    compile("build/named2b", main)
+    compile("build/named2b", main, output="verilog")
     assert check_files_equal(__file__, "build/named2b.v", "gold/named2b.v")
 
 
@@ -53,5 +53,5 @@ def test_named4():
     a(I0=main.I[0])
     wire(a.O, main.O)
 
-    compile("build/named2c", main)
+    compile("build/named2c", main, output="verilog")
     assert check_files_equal(__file__, "build/named2c.v", "gold/named2c.v")