Merge 034d99a into f8327e8

.travis.yml

@@ -26,7 +26,7 @@ jobs:
       script:
           # TODO: Enable pep8 check
           # - py.test --cov magma --pep8 magma -v --cov-report term-missing tests
-          - py.test --cov magma -v --cov-report term-missing tests
+          - py.test -s -vv --cov magma -v --cov-report term-missing tests
     - stage: trigger downstream
       script: |
         # See https://github.com/mernst/plume-lib/blob/master/bin/trigger-travis.sh for documentation

magma/backend/blif.py

@@ -5,7 +5,7 @@
 from ..array import ArrayType
 from ..port import INPUT, OUTPUT, INOUT
 from ..clock import wiredefaultclock
-from ..circuit import *
+from ..is_definition import isdefinition
 
 __all__ = ['compile']
 

magma/backend/verilog.py

@@ -10,7 +10,7 @@
 from ..clock import ClockType, EnableType, ResetType
 from ..array import ArrayKind, ArrayType
 from ..bits import SIntType
-from ..circuit import *
+from ..is_definition import isdefinition
 from ..clock import wiredefaultclock
 import logging
 import os

magma/circuit.py

@@ -16,6 +16,7 @@
 from .debug import get_callee_frame_info, debug_info
 from .logging import warning
 from .port import report_wiring_warning
+from .is_definition import isdefinition
 
 __all__  = ['AnonymousCircuitType']
 __all__ += ['AnonymousCircuit']
@@ -27,8 +28,6 @@
 __all__ += ['getCurrentDefinition']
 __all__ += ['magma_clear_circuit_cache']
 
-__all__ += ['isdefinition']
-__all__ += ['isprimitive']
 __all__ += ['CopyInstance']
 __all__ += ['circuit_type_method']
 __all__ += ['circuit_generator']
@@ -390,14 +389,6 @@ def popDefinition():
     else:
         currentDefinition = None
 
-#  A circuit is a definition if it has instances
-def isdefinition(circuit):
-    'Return whether a circuit is a module definition'
-    return getattr(circuit, "is_definition", False)
-
-def isprimitive(circuit):
-    return getattr(circuit, "primitive", False)
-
 # a map from circuitDefinition names to circuit definition objects
 definitionCache = {}
 

magma/compile.py

@@ -7,7 +7,7 @@
 from .backend import verilog, blif, firrtl, dot
 from .config import get_compile_dir
 from .logging import error
-from .circuit import isdefinition
+from .is_definition import isdefinition
 from .logging import warning
 import magma as m
 

magma/is_definition.py

@@ -0,0 +1,4 @@
+#  A circuit is a definition if it has instances
+def isdefinition(circuit):
+    'Return whether a circuit is a module definition'
+    return getattr(circuit, "is_definition", False)

magma/passes/clock.py

@@ -1,4 +1,4 @@
-from ..circuit import isdefinition
+from ..is_definition import isdefinition
 from ..clock import wiredefaultclock
 from .passes import DefinitionPass
 

magma/passes/passes.py

@@ -1,4 +1,4 @@
-from ..circuit import isdefinition
+from ..is_definition import isdefinition
 from .tsort import tsort
 
 __all__ = ['Pass', 'InstancePass', 'DefinitionPass', 'InstanceGraphPass']

magma/simulator/mdb.py

@@ -1,7 +1,7 @@
 from __future__ import print_function
 from .python_simulator import PythonSimulator
 from ..passes.debug_name import DebugNamePass
-from ..circuit import *
+from ..is_definition import isdefinition
 from ..scope import *
 from ..array import ArrayType
 from ..bit import BitType

magma/transforms.py

@@ -1,5 +1,7 @@
 from collections import namedtuple, OrderedDict
-from .circuit import *
+from .circuit import DefineCircuit, EndCircuit, CopyInstance
+from .is_definition import isdefinition
+from .is_primitive import isprimitive
 from .bit import *
 from .clock import ClockType, EnableType, ResetType, AsyncResetType, wiredefaultclock
 from .array import *

tests/test_circuit/test_is_definition.py

@@ -1,5 +1,5 @@
 from magma import *
-from magma.circuit import isdefinition
+from magma.is_definition import isdefinition
 
 
 def test_is_definition():

tests/test_verilog/build/test_rxmod_module_arg.v

@@ -0,0 +1,53 @@
+module RXMOD(
+  input RX, 
+  input CLK,
+  output [7:0] data,
+  output valid);
+
+reg RX_1;
+reg RX_2;
+always @(posedge CLK) begin
+  RX_1 <= RX;
+  RX_2 <= RX_1;
+end
+
+wire RXi;
+assign RXi = RX_2;
+
+reg [8:0] dataReg;
+reg validReg = 0;
+assign data = dataReg[7:0];
+assign valid = validReg;
+
+reg [12:0] readClock = 0; // which subclock?
+reg [3:0] readBit = 0; // which bit? (0-8)
+reg reading = 0;
+
+
+always @ (posedge CLK)
+begin
+  if(RXi==0 && reading==0) begin
+    reading <= 1;
+    readClock <= 150; // sample to middle of second byte
+    readBit <= 0;
+    validReg <= 0;
+  end else if(reading==1 && readClock==0 && readBit==8) begin
+    // we're done
+    reading <= 0;
+    dataReg[8] <= RXi;
+    validReg <= 1;
+  end else if(reading==1 && readClock==0) begin
+    // read a byte
+    dataReg[readBit] <= RXi;
+    readClock <= 100;
+    readBit <= readBit + 1;
+    validReg <= 0;
+  end else if(reading==1 && readClock>0) begin
+    readClock <= readClock - 1;
+    validReg <= 0;
+  end else begin
+    validReg <= 0;
+  end
+end
+endmodule
+