Merge pull request #368 from phanrahan/fix-bit-vector

Fix bit vector
phanrahan · Mar 13, 2019 · 1a0f153 · 1a0f153
2 parents 189d0b2 + 07016fb
commit 1a0f153
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Showing 10 changed files with 266 additions and 22 deletions.
diff --git a/magma/backend/coreir_.py b/magma/backend/coreir_.py
@@ -1,5 +1,5 @@
 from collections import OrderedDict
-from bit_vector import BitVector
+from hwtypes import BitVector
 import os
 from ..bit import VCC, GND, BitType, BitIn, BitOut, MakeBit, BitKind
 from ..array import ArrayKind, ArrayType, Array
@@ -199,7 +199,7 @@ def compile_instance(self, instance, module_definition):
                 if name in {"name", "loc"}:
                     continue  # Skip
                 elif isinstance(value, tuple):
-                    args[name] = BitVector(value[0], num_bits=value[1])
+                    args[name] = BitVector[value[1]](value[0])
                 else:
                     args[name] = value
             args = self.context.new_values(args)

diff --git a/magma/bits.py b/magma/bits.py
@@ -4,7 +4,7 @@
 from .array import ArrayType, ArrayKind
 from .debug import debug_wire
 
-from bit_vector import BitVector, SIntVector
+from hwtypes import BitVector, SIntVector
 
 __all__ = ['Bits', 'BitsType', 'BitsKind']
 __all__ += ['UInt', 'UIntType', 'UIntKind']

diff --git a/magma/simulator/python_simulator.py b/magma/simulator/python_simulator.py
@@ -14,7 +14,7 @@
 from ..bit import VCC, GND, BitType, _BitType
 from ..array import ArrayType
 from ..bits import SIntType, BitsType, UIntType
-from bit_vector import BitVector
+from hwtypes import BitVector
 from ..bitutils import seq2int
 from ..clock import ClockType
 
@@ -140,9 +140,10 @@ def set_value(self, bit, newval):
             elif isinstance(bit, BitsType) and isinstance(newval, int):
                 if not isinstance(bit, SIntType) and newval < 0:
                     raise ValueError(f"Can only set {bit} of type {type(bit)} with positive integer, not {newval}")
-                newval = BitVector(newval, len(bit))
+                newval = BitVector[len(bit)](newval).as_bool_list()
             elif not isinstance(newval, list):
                 raise TypeError(f"Calling set_value with {bit} of type {type(bit)} only works with a list of values or a BitVector")
+
             for b,v in zip(bit, newval):
                 self.set_value(b, v)
             return
@@ -381,7 +382,7 @@ def __call__(self, *largs):
                 val = largs[j]
                 if isinstance(port, ArrayType):
                     n = type(port).N
-                    val = BitVector(val, num_bits=n)
+                    val = BitVector[n](val)
                 self.set_value(getattr(circuit, name), val)
                 j += 1
 

diff --git a/magma/testing/coroutine.py b/magma/testing/coroutine.py
@@ -1,5 +1,5 @@
 from magma.simulator import PythonSimulator
-from bit_vector import BitVector
+from hwtypes import BitVector
 
 class Coroutine:
     """

diff --git a/setup.py b/setup.py
@@ -32,7 +32,7 @@
         "numpy",
         "graphviz",
         "coreir>=1.0.*",
-        "bit_vector==0.42a0"
+        "hwtypes>=1.0.*"
     ],
     python_requires='>=3.6',
     long_description=long_description,

diff --git a/tests/test_coreir/test_coreir.py b/tests/test_coreir/test_coreir.py
@@ -60,4 +60,4 @@ def test_nested_clocks():
     test_circuit = DefineCircuit('test_nested_clocks', *args)
     inner_test_circuit()
     EndCircuit()
-    GetCoreIRModule(cirb, test_circuit)
+    GetCoreIRModule(cirb, test_circuit)
diff --git a/tests/test_simulator/test_values.py b/tests/test_simulator/test_values.py
@@ -1,6 +1,6 @@
 from magma.simulator.python_simulator import PythonSimulator
 import magma as m
-from bit_vector import BitVector as BV
+from hwtypes import BitVector
 import pytest
 
 
@@ -35,7 +35,7 @@ def definition(io):
 
     sim = PythonSimulator(Main)
     for value in range(0, 4):
-        bv = BV(value, 2)
+        bv = BitVector[2](value)
         bools = bv.as_bool_list()
         sim.set_value(Main.I, bools)
         sim.evaluate()
@@ -63,7 +63,7 @@ def definition(io):
 
     sim = PythonSimulator(Main)
     for value in range(0, 4):
-        bv = BV(value, 2)
+        bv = BitVector[2](value)
         bools = bv.as_bool_list()
         sim.set_value(Main.I, bools)
         sim.evaluate()
@@ -88,7 +88,7 @@ def definition(io):
 
     sim = PythonSimulator(Main)
     for value in range(-2, 2):
-        bv = BV(value, 2)
+        bv = BitVector[2](value)
         bools = bv.as_bool_list()
         sim.set_value(Main.I, bools)
         sim.evaluate()

diff --git a/tests/test_syntax/TestBasic_driver.cpp b/tests/test_syntax/TestBasic_driver.cpp
@@ -0,0 +1,112 @@
+#include "VTestBasic.h"
+#include "verilated.h"
+#include <iostream>
+#include <verilated_vcd_c.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+// Based on https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONNECTING-TO-C
+vluint64_t main_time = 0;       // Current simulation time
+// This is a 64-bit integer to reduce wrap over issues and
+// allow modulus.  You can also use a double, if you wish.
+
+double sc_time_stamp () {       // Called by $time in Verilog
+    return main_time;           // converts to double, to match
+                                // what SystemC does
+}
+
+#if VM_TRACE
+VerilatedVcdC* tracer;
+#endif
+
+void my_assert(
+    unsigned int got,
+    unsigned int expected,
+    int i,
+    const char* port) {
+  if (got != expected) {
+    std::cerr << std::endl;  // end the current line
+    std::cerr << "Got      : 0x" << std::hex << got << std::endl;
+    std::cerr << "Expected : 0x" << std::hex << expected << std::endl;
+    std::cerr << "i        : " << std::dec << i << std::endl;
+    std::cerr << "Port     : " << port << std::endl;
+#if VM_TRACE
+    tracer->close();
+#endif
+    exit(1);
+  }
+}
+
+int main(int argc, char **argv) {
+  Verilated::commandArgs(argc, argv);
+  VTestBasic* top = new VTestBasic;
+
+#if VM_TRACE
+  Verilated::traceEverOn(true);
+  tracer = new VerilatedVcdC;
+  top->trace(tracer, 99);
+  mkdir("logs", S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH);
+  tracer->open("logs/TestBasic.vcd");
+#endif
+
+  top->I = 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->I = 2;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  my_assert(top->O, 1, 4, "TestBasic.O");
+  top->I = 3;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  my_assert(top->O, 2, 7, "TestBasic.O");
+  top->I = 0;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  my_assert(top->O, 3, 10, "TestBasic.O");
+
+
+#if VM_TRACE
+  tracer->close();
+#endif
+}
diff --git a/tests/test_syntax/TestShiftRegister_driver.cpp b/tests/test_syntax/TestShiftRegister_driver.cpp
@@ -0,0 +1,112 @@
+#include "VTestShiftRegister.h"
+#include "verilated.h"
+#include <iostream>
+#include <verilated_vcd_c.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+// Based on https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONNECTING-TO-C
+vluint64_t main_time = 0;       // Current simulation time
+// This is a 64-bit integer to reduce wrap over issues and
+// allow modulus.  You can also use a double, if you wish.
+
+double sc_time_stamp () {       // Called by $time in Verilog
+    return main_time;           // converts to double, to match
+                                // what SystemC does
+}
+
+#if VM_TRACE
+VerilatedVcdC* tracer;
+#endif
+
+void my_assert(
+    unsigned int got,
+    unsigned int expected,
+    int i,
+    const char* port) {
+  if (got != expected) {
+    std::cerr << std::endl;  // end the current line
+    std::cerr << "Got      : 0x" << std::hex << got << std::endl;
+    std::cerr << "Expected : 0x" << std::hex << expected << std::endl;
+    std::cerr << "i        : " << std::dec << i << std::endl;
+    std::cerr << "Port     : " << port << std::endl;
+#if VM_TRACE
+    tracer->close();
+#endif
+    exit(1);
+  }
+}
+
+int main(int argc, char **argv) {
+  Verilated::commandArgs(argc, argv);
+  VTestShiftRegister* top = new VTestShiftRegister;
+
+#if VM_TRACE
+  Verilated::traceEverOn(true);
+  tracer = new VerilatedVcdC;
+  top->trace(tracer, 99);
+  mkdir("logs", S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH);
+  tracer->open("logs/TestShiftRegister.vcd");
+#endif
+
+  top->I = 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->I = 2;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  my_assert(top->O, 1, 4, "TestShiftRegister.O");
+  top->I = 3;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  my_assert(top->O, 2, 7, "TestShiftRegister.O");
+  top->I = 0;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  top->eval();
+  main_time++;
+  #if VM_TRACE
+  tracer->dump(main_time);
+  #endif
+  top->CLK ^= 1;
+  my_assert(top->O, 3, 10, "TestShiftRegister.O");
+
+
+#if VM_TRACE
+  tracer->close();
+#endif
+}