Change attribute name to be more explicit

phanrahan · Oct 21, 2019 · 1e0ccda · 1e0ccda
1 parent c7726b9
commit 1e0ccda
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/magma/backend/coreir_.py b/magma/backend/coreir_.py
@@ -255,9 +255,9 @@ def compile_declaration(self, declaration):
             module_type = self.context.Flip(module_type)
 
         kwargs = {}
-        if hasattr(declaration, "verilog_param_types"):
+        if hasattr(declaration, "coreir_config_param_types"):
             kwargs["cparams"] = \
-                self.make_cparams(declaration.verilog_param_types)
+                self.make_cparams(declaration.coreir_config_param_types)
 
         coreir_module = \
             self.context.global_namespace.new_module(declaration.coreir_name,
@@ -329,9 +329,9 @@ def compile_definition(self, definition):
         self.check_interface(definition)
         module_type = self.convert_interface_to_module_type(definition.interface)
         kwargs = {}
-        if hasattr(definition, "verilog_param_types"):
+        if hasattr(definition, "coreir_config_param_types"):
             kwargs["cparams"] = \
-                self.make_cparams(definition.verilog_param_types)
+                self.make_cparams(definition.coreir_config_param_types)
 
         coreir_module = \
             self.context.global_namespace.new_module(definition.coreir_name,

diff --git a/magma/fromverilog.py b/magma/fromverilog.py
@@ -187,7 +187,7 @@ def _get_lines(start_line, end_line):
         parsed_name, args = ParseVerilogModule(verilog_defn, type_map)
         assert parsed_name == name
         magma_defn = func(name, *args)
-        magma_defn.verilog_param_types = param_map
+        magma_defn.coreir_config_param_types = param_map
         if func == DefineCircuit:
             # Attach relevant lines of verilog source.
             magma_defn.verilogFile = _get_lines(