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Make coreir-verilog inline a generic option
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Making inline verilog through coreir an option, rather than its own
compilation target.
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rsetaluri committed Sep 7, 2018
1 parent a76b492 commit 248c510
Showing 1 changed file with 2 additions and 6 deletions.
8 changes: 2 additions & 6 deletions magma/compile.py
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,8 @@ def __compile_to_coreir(main, file_name, opts):
cmd += f" -o \"{split}/*.v\" -s"
else:
cmd += f" -o {file_name}.v"
if "inline" in opts and opts["inline"]:
cmd += " --inline"
subprocess.run(cmd, shell=True)


Expand Down Expand Up @@ -108,12 +110,6 @@ def compile(basename, main, output='verilog', **kwargs):
write_file(file_name, 'fir', firrtl.compile(main))
elif output == 'coreir':
__compile_to_coreir(main, file_name, opts)
elif output == 'coreir-verilog-inline':
# underscore so our coreir module doesn't conflict with coreir bindings
# package
from .backend import coreir_
coreir_.compile(main, file_name + ".json")
subprocess.run(f"coreir -l commonlib -i {file_name}.json -o {file_name}.v --inline", shell=True)
elif output == 'dot':
write_file(file_name, 'dot', dot.compile(main))
else:
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