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Stub out operators
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@leonardt
leonardt committed Jun 12, 2019
1 parent 73e03b7 commit 340836f
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Showing 3 changed files with 348 additions and 393 deletions.
217 changes: 98 additions & 119 deletions tests/test_syntax/gold/RegisterMode.json
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Original file line number Diff line number Diff line change
Expand Up @@ -175,80 +175,80 @@
"genargs":{"width":["Int",2]},
"modargs":{"value":[["BitVector",2],"2'h1"]}
},
"corebit_eq_inst0":{
"modref":"global.corebit_eq"
},
"corebit_eq_inst1":{
"modref":"global.corebit_eq"
},
"corebit_eq_inst2":{
"modref":"global.corebit_eq"
},
"corebit_eq_inst3":{
"modref":"global.corebit_eq"
},
"corebit_eq_inst4":{
"modref":"global.corebit_eq"
},
"corebit_eq_inst5":{
"modref":"global.corebit_eq"
},
"corebit_eq_inst6":{
"modref":"global.corebit_eq"
},
"coreir_eq_2_inst0":{
"eq_inst0":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst1":{
"eq_inst1":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst10":{
"eq_inst10":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst11":{
"eq_inst11":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst12":{
"eq_inst12":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst13":{
"eq_inst13":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst2":{
"eq_inst14":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst3":{
"eq_inst15":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst4":{
"eq_inst16":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst5":{
"eq_inst17":{
"modref":"corebit.and"
},
"eq_inst18":{
"modref":"corebit.and"
},
"eq_inst19":{
"modref":"corebit.and"
},
"eq_inst2":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst6":{
"eq_inst20":{
"modref":"corebit.and"
},
"eq_inst3":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst7":{
"eq_inst4":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst8":{
"eq_inst5":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
},
"coreir_eq_2_inst9":{
"eq_inst6":{
"modref":"corebit.and"
},
"eq_inst7":{
"modref":"corebit.and"
},
"eq_inst8":{
"modref":"corebit.and"
},
"eq_inst9":{
"genref":"coreir.eq",
"genargs":{"width":["Int",2]}
}
Expand All @@ -257,112 +257,112 @@
["self.clk_en","Mux2_inst0.I0"],
["bit_const_0_None.out","Mux2_inst0.I1"],
["Mux2_inst1.I0","Mux2_inst0.O"],
["coreir_eq_2_inst1.out","Mux2_inst0.S"],
["eq_inst1.out","Mux2_inst0.S"],
["bit_const_0_None.out","Mux2_inst1.I1"],
["Mux2_inst2.I0","Mux2_inst1.O"],
["coreir_eq_2_inst4.out","Mux2_inst1.S"],
["eq_inst4.out","Mux2_inst1.S"],
["bit_const_1_None.out","Mux2_inst2.I1"],
["corebit_eq_inst1.O","Mux2_inst2.S"],
["eq_inst7.out","Mux2_inst2.S"],
["self.clk_en","Mux2_inst3.I0"],
["bit_const_0_None.out","Mux2_inst3.I1"],
["Mux2_inst4.I0","Mux2_inst3.O"],
["coreir_eq_2_inst7.out","Mux2_inst3.S"],
["eq_inst10.out","Mux2_inst3.S"],
["bit_const_0_None.out","Mux2_inst4.I1"],
["Mux2_inst5.I0","Mux2_inst4.O"],
["coreir_eq_2_inst11.out","Mux2_inst4.S"],
["eq_inst14.out","Mux2_inst4.S"],
["bit_const_1_None.out","Mux2_inst5.I1"],
["self.O1","Mux2_inst5.O"],
["corebit_eq_inst4.O","Mux2_inst5.S"],
["eq_inst18.out","Mux2_inst5.S"],
["self.value","Mux2_x4_inst0.I0"],
["self.value","Mux2_x4_inst0.I1"],
["Mux2_x4_inst2.I0","Mux2_x4_inst0.O"],
["coreir_eq_2_inst0.out","Mux2_x4_inst0.S"],
["eq_inst0.out","Mux2_x4_inst0.S"],
["self.self_register_O","Mux2_x4_inst1.I0"],
["self.self_register_O","Mux2_x4_inst1.I1"],
["Mux2_x4_inst3.I0","Mux2_x4_inst1.O"],
["coreir_eq_2_inst2.out","Mux2_x4_inst1.S"],
["eq_inst2.out","Mux2_x4_inst1.S"],
["Mux2_x4_inst7.O","Mux2_x4_inst10.I0"],
["self.const_","Mux2_x4_inst10.I1"],
["Mux2_x4_inst13.I0","Mux2_x4_inst10.O"],
["coreir_eq_2_inst12.out","Mux2_x4_inst10.S"],
["eq_inst15.out","Mux2_x4_inst10.S"],
["Mux2_x4_inst8.O","Mux2_x4_inst11.I0"],
["self.self_register_O","Mux2_x4_inst11.I1"],
["Mux2_x4_inst14.I0","Mux2_x4_inst11.O"],
["coreir_eq_2_inst13.out","Mux2_x4_inst11.S"],
["eq_inst16.out","Mux2_x4_inst11.S"],
["Mux2_x4_inst9.O","Mux2_x4_inst12.I0"],
["self.config_data","Mux2_x4_inst12.I1"],
["self.O0","Mux2_x4_inst12.O"],
["corebit_eq_inst3.O","Mux2_x4_inst12.S"],
["eq_inst17.out","Mux2_x4_inst12.S"],
["self.self_register_O","Mux2_x4_inst13.I1"],
["self.O2","Mux2_x4_inst13.O"],
["corebit_eq_inst5.O","Mux2_x4_inst13.S"],
["eq_inst19.out","Mux2_x4_inst13.S"],
["self.self_register_O","Mux2_x4_inst14.I1"],
["self.O3","Mux2_x4_inst14.O"],
["corebit_eq_inst6.O","Mux2_x4_inst14.S"],
["eq_inst20.out","Mux2_x4_inst14.S"],
["self.value","Mux2_x4_inst2.I1"],
["Mux2_x4_inst4.I0","Mux2_x4_inst2.O"],
["coreir_eq_2_inst3.out","Mux2_x4_inst2.S"],
["eq_inst3.out","Mux2_x4_inst2.S"],
["self.self_register_O","Mux2_x4_inst3.I1"],
["Mux2_x4_inst5.I0","Mux2_x4_inst3.O"],
["coreir_eq_2_inst5.out","Mux2_x4_inst3.S"],
["eq_inst5.out","Mux2_x4_inst3.S"],
["self.config_data","Mux2_x4_inst4.I1"],
["corebit_eq_inst0.O","Mux2_x4_inst4.S"],
["eq_inst6.out","Mux2_x4_inst4.S"],
["self.self_register_O","Mux2_x4_inst5.I1"],
["corebit_eq_inst2.O","Mux2_x4_inst5.S"],
["eq_inst8.out","Mux2_x4_inst5.S"],
["self.value","Mux2_x4_inst6.I0"],
["self.value","Mux2_x4_inst6.I1"],
["Mux2_x4_inst9.I0","Mux2_x4_inst6.O"],
["coreir_eq_2_inst6.out","Mux2_x4_inst6.S"],
["eq_inst9.out","Mux2_x4_inst6.S"],
["self.self_register_O","Mux2_x4_inst7.I0"],
["self.value","Mux2_x4_inst7.I1"],
["coreir_eq_2_inst8.out","Mux2_x4_inst7.S"],
["eq_inst11.out","Mux2_x4_inst7.S"],
["self.self_register_O","Mux2_x4_inst8.I0"],
["self.self_register_O","Mux2_x4_inst8.I1"],
["coreir_eq_2_inst9.out","Mux2_x4_inst8.S"],
["eq_inst12.out","Mux2_x4_inst8.S"],
["self.value","Mux2_x4_inst9.I1"],
["coreir_eq_2_inst10.out","Mux2_x4_inst9.S"],
["corebit_eq_inst0.I1","bit_const_1_None.out"],
["corebit_eq_inst1.I1","bit_const_1_None.out"],
["corebit_eq_inst2.I1","bit_const_1_None.out"],
["corebit_eq_inst3.I1","bit_const_1_None.out"],
["corebit_eq_inst4.I1","bit_const_1_None.out"],
["corebit_eq_inst5.I1","bit_const_1_None.out"],
["corebit_eq_inst6.I1","bit_const_1_None.out"],
["coreir_eq_2_inst10.in1","const_0_2.out"],
["coreir_eq_2_inst11.in1","const_0_2.out"],
["coreir_eq_2_inst12.in1","const_0_2.out"],
["coreir_eq_2_inst13.in1","const_0_2.out"],
["coreir_eq_2_inst3.in1","const_0_2.out"],
["coreir_eq_2_inst4.in1","const_0_2.out"],
["coreir_eq_2_inst5.in1","const_0_2.out"],
["coreir_eq_2_inst0.in1","const_1_2.out"],
["coreir_eq_2_inst1.in1","const_1_2.out"],
["coreir_eq_2_inst2.in1","const_1_2.out"],
["coreir_eq_2_inst6.in1","const_1_2.out"],
["coreir_eq_2_inst7.in1","const_1_2.out"],
["coreir_eq_2_inst8.in1","const_1_2.out"],
["coreir_eq_2_inst9.in1","const_1_2.out"],
["self.config_we","corebit_eq_inst0.I0"],
["self.config_we","corebit_eq_inst1.I0"],
["self.config_we","corebit_eq_inst2.I0"],
["self.config_we","corebit_eq_inst3.I0"],
["self.config_we","corebit_eq_inst4.I0"],
["self.config_we","corebit_eq_inst5.I0"],
["self.config_we","corebit_eq_inst6.I0"],
["self.mode","coreir_eq_2_inst0.in0"],
["self.mode","coreir_eq_2_inst1.in0"],
["self.mode","coreir_eq_2_inst10.in0"],
["self.mode","coreir_eq_2_inst11.in0"],
["self.mode","coreir_eq_2_inst12.in0"],
["self.mode","coreir_eq_2_inst13.in0"],
["self.mode","coreir_eq_2_inst2.in0"],
["self.mode","coreir_eq_2_inst3.in0"],
["self.mode","coreir_eq_2_inst4.in0"],
["self.mode","coreir_eq_2_inst5.in0"],
["self.mode","coreir_eq_2_inst6.in0"],
["self.mode","coreir_eq_2_inst7.in0"],
["self.mode","coreir_eq_2_inst8.in0"],
["self.mode","coreir_eq_2_inst9.in0"]
["eq_inst13.out","Mux2_x4_inst9.S"],
["eq_inst17.in1","bit_const_1_None.out"],
["eq_inst18.in1","bit_const_1_None.out"],
["eq_inst19.in1","bit_const_1_None.out"],
["eq_inst20.in1","bit_const_1_None.out"],
["eq_inst6.in1","bit_const_1_None.out"],
["eq_inst7.in1","bit_const_1_None.out"],
["eq_inst8.in1","bit_const_1_None.out"],
["eq_inst13.in1","const_0_2.out"],
["eq_inst14.in1","const_0_2.out"],
["eq_inst15.in1","const_0_2.out"],
["eq_inst16.in1","const_0_2.out"],
["eq_inst3.in1","const_0_2.out"],
["eq_inst4.in1","const_0_2.out"],
["eq_inst5.in1","const_0_2.out"],
["eq_inst0.in1","const_1_2.out"],
["eq_inst1.in1","const_1_2.out"],
["eq_inst10.in1","const_1_2.out"],
["eq_inst11.in1","const_1_2.out"],
["eq_inst12.in1","const_1_2.out"],
["eq_inst2.in1","const_1_2.out"],
["eq_inst9.in1","const_1_2.out"],
["self.mode","eq_inst0.in0"],
["self.mode","eq_inst1.in0"],
["self.mode","eq_inst10.in0"],
["self.mode","eq_inst11.in0"],
["self.mode","eq_inst12.in0"],
["self.mode","eq_inst13.in0"],
["self.mode","eq_inst14.in0"],
["self.mode","eq_inst15.in0"],
["self.mode","eq_inst16.in0"],
["self.config_we","eq_inst17.in0"],
["self.config_we","eq_inst18.in0"],
["self.config_we","eq_inst19.in0"],
["self.mode","eq_inst2.in0"],
["self.config_we","eq_inst20.in0"],
["self.mode","eq_inst3.in0"],
["self.mode","eq_inst4.in0"],
["self.mode","eq_inst5.in0"],
["self.config_we","eq_inst6.in0"],
["self.config_we","eq_inst7.in0"],
["self.config_we","eq_inst8.in0"],
["self.mode","eq_inst9.in0"]
]
},
"Register_comb":{
Expand All @@ -385,27 +385,6 @@
["self.en","Mux2_x4_inst0.S"],
["self.self_value_O","self.O1"]
]
},
"corebit_eq":{
"type":["Record",[
["I0","BitIn"],
["I1","BitIn"],
["O","Bit"]
]],
"instances":{
"not_inst0":{
"modref":"corebit.not"
},
"xor_inst0":{
"modref":"corebit.xor"
}
},
"connections":[
["xor_inst0.out","not_inst0.in"],
["self.O","not_inst0.out"],
["xor_inst0.in0","self.I0"],
["xor_inst0.in1","self.I1"]
]
}
}
}
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