Merge a45f99e into 3cbd73a

magma/backend/coreir_.py

@@ -210,6 +210,8 @@ def compile_instance(self, instance, module_definition):
             for name, value in type(instance).coreir_genargs.items():
                 if isinstance(value, AsyncResetKind):
                     value = self.context.named_types["coreir", "arst"]
+                elif isinstance(value, ClockKind):
+                    value = self.context.named_types["coreir", "clk"]
                 gen_args[name] = value
             gen_args = self.context.new_values(gen_args)
             return module_definition.add_generator_instance(instance.name,

tests/test_type/test_clock.py

@@ -1,7 +1,12 @@
+import pytest
+import tempfile
 from magma import In, Out, Flip, \
     Clock, ClockType, ClockKind, \
-    Reset, ResetType, ResetKind, \
-    Enable, EnableType, EnableKind
+    Reset, ResetType, ResetKind, reset \
+    Enable, EnableType, EnableKind, enable \
+    AsyncReset, AsyncResetType, AsyncResetKind, \
+    DeclareCircuit, DefineCircuit, EndCircuit, \
+    Bit, bit, wire, compile
 
 def test_clock():
     assert isinstance(Clock, ClockKind)
@@ -114,3 +119,58 @@ def test_enable_val():
     assert isinstance(b, Enable)
     assert not b.isinput()
     assert not b.isoutput()
+
+@pytest.mark.parametrize("T", [Clock, AsyncReset])
+def test_coreir_wrap(T):
+    def define_wrap(type_, type_name, in_type):
+        def sim_wrap(self, value_store, state_store):
+            input_val = value_store.get_value(getattr(self, "in"))
+            value_store.set_value(self.out, input_val)
+
+        return DeclareCircuit(
+            f'coreir_wrap{type_name}',
+            "in", In(in_type), "out", Out(type_),
+            coreir_genargs = {"type": type_},
+            coreir_name="wrap",
+            coreir_lib="coreir",
+            simulate=sim_wrap
+        )
+
+    foo = DefineCircuit("foo", "r", In(T))
+    EndCircuit()
+
+    top = DefineCircuit("top", "O", Out(Bit))
+    foo_inst = foo()
+    wrap = define_wrap(T, "Bit", Bit)()
+    wire(bit(0), wrap.interface.ports["in"])
+    wire(wrap.out, foo_inst.r)
+    wire(bit(0), top.O)
+    EndCircuit()
+
+    with tempfile.TemporaryDirectory() as tempdir:
+        filename = f"{tempdir}/top"
+        compile(filename, top, output="coreir")
+        got = open(f"{filename}.json").read()
+    expected_filename = f"tests/test_type/test_coreir_wrap_golden_{T}.json"
+    expected = open(expected_filename).read()
+    assert got == expected
+
+
+@pytest.mark.parametrize("T,t", [(Reset, reset), (Enable, enable)])
+def test_const_wire(T, t):
+    foo = DefineCircuit("foo", "I", In(T))
+    EndCircuit()
+
+    top = DefineCircuit("top", "O", Out(Bit))
+    foo_inst = foo()
+    wire(t(0), foo_inst.I)
+    wire(bit(0), top.O)
+    EndCircuit()
+
+    with tempfile.TemporaryDirectory() as tempdir:
+        filename = f"{tempdir}/top"
+        compile(filename, top, output="coreir")
+        got = open(f"{filename}.json").read()
+    expected_filename = f"tests/test_type/test_const_wire_golden.json"
+    expected = open(expected_filename).read()
+    assert got == expected

tests/test_type/test_const_wire_golden.json

@@ -0,0 +1,31 @@
+{"top":"global.top",
+"namespaces":{
+  "global":{
+    "modules":{
+      "foo":{
+        "type":["Record",[
+          ["I","BitIn"]
+        ]]
+      },
+      "top":{
+        "type":["Record",[
+          ["O","Bit"]
+        ]],
+        "instances":{
+          "bit_const_0_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",false]}
+          },
+          "inst0":{
+            "modref":"global.foo"
+          }
+        },
+        "connections":[
+          ["inst0.I","bit_const_0_None.out"],
+          ["self.O","bit_const_0_None.out"]
+        ]
+      }
+    }
+  }
+}
+}

tests/test_type/test_coreir_wrap_golden.json

@@ -0,0 +1,35 @@
+{"top":"global.top",
+"namespaces":{
+  "global":{
+    "modules":{
+      "foo":{
+        "type":["Record",[
+          ["r",["Named","coreir.arstIn"]]
+        ]]
+      },
+      "top":{
+        "type":["Record",[
+          ["O","Bit"]
+        ]],
+        "instances":{
+          "bit_const_0_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",false]}
+          },
+          "inst0":{
+            "modref":"global.foo"
+          },
+          "inst1":{
+            "genref":"coreir.wrap",
+            "genargs":{"type":["CoreIRType",["Named","coreir.arst"]]}
+          }
+        },
+        "connections":[
+          ["inst1.in","bit_const_0_None.out"],
+          ["self.O","bit_const_0_None.out"],
+          ["inst1.out","inst0.r"]
+        ]
+      }
+    }
+  }
+}

tests/test_type/test_coreir_wrap_golden_AsyncReset.json

@@ -0,0 +1,36 @@
+{"top":"global.top",
+"namespaces":{
+  "global":{
+    "modules":{
+      "foo":{
+        "type":["Record",[
+          ["r",["Named","coreir.arstIn"]]
+        ]]
+      },
+      "top":{
+        "type":["Record",[
+          ["O","Bit"]
+        ]],
+        "instances":{
+          "bit_const_0_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",false]}
+          },
+          "inst0":{
+            "modref":"global.foo"
+          },
+          "inst1":{
+            "genref":"coreir.wrap",
+            "genargs":{"type":["CoreIRType",["Named","coreir.arst"]]}
+          }
+        },
+        "connections":[
+          ["inst1.in","bit_const_0_None.out"],
+          ["self.O","bit_const_0_None.out"],
+          ["inst1.out","inst0.r"]
+        ]
+      }
+    }
+  }
+}
+}

tests/test_type/test_coreir_wrap_golden_Clock.json

@@ -0,0 +1,36 @@
+{"top":"global.top",
+"namespaces":{
+  "global":{
+    "modules":{
+      "foo":{
+        "type":["Record",[
+          ["r",["Named","coreir.clkIn"]]
+        ]]
+      },
+      "top":{
+        "type":["Record",[
+          ["O","Bit"]
+        ]],
+        "instances":{
+          "bit_const_0_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",false]}
+          },
+          "inst0":{
+            "modref":"global.foo"
+          },
+          "inst1":{
+            "genref":"coreir.wrap",
+            "genargs":{"type":["CoreIRType",["Named","coreir.clk"]]}
+          }
+        },
+        "connections":[
+          ["inst1.in","bit_const_0_None.out"],
+          ["self.O","bit_const_0_None.out"],
+          ["inst1.out","inst0.r"]
+        ]
+      }
+    }
+  }
+}
+}