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Merge pull request #350 from phanrahan/repr-hash
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Repr hash
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leonardt committed Feb 12, 2019
2 parents aae1977 + a080f7c commit 355f2a0
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Showing 4 changed files with 137 additions and 1 deletion.
4 changes: 3 additions & 1 deletion magma/circuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,6 @@ def __str__(cls):
return f"{cls.__name__}{interface}"

def __repr__(cls):

name = cls.__name__
args = str(cls.IO)
if hasattr(cls,"instances"):
Expand All @@ -136,6 +135,9 @@ def __repr__(cls):

return s

def __hash__(cls):
return hash(repr(cls))

def _repr_html_(cls):
return circuit_to_html(cls)

Expand Down
36 changes: 36 additions & 0 deletions tests/gold/uniquify_equal.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
{"top":"global.top",
"namespaces":{
"global":{
"modules":{
"foo":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"connections":[
["self.O","self.I"]
]
},
"top":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"instances":{
"foo_inst0":{
"modref":"global.foo"
},
"foo_inst1":{
"modref":"global.foo"
}
},
"connections":[
["self.I","foo_inst0.I"],
["foo_inst1.I","foo_inst0.O"],
["self.O","foo_inst1.O"]
]
}
}
}
}
}
46 changes: 46 additions & 0 deletions tests/gold/uniquify_unequal.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
{"top":"global.top",
"namespaces":{
"global":{
"modules":{
"foo":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"connections":[
["self.O","self.I"]
]
},
"foo_unq1":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["O",["Array",2,"Bit"]]
]],
"connections":[
["self.O","self.I"]
]
},
"top":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"instances":{
"foo_inst0":{
"modref":"global.foo"
},
"foo_inst1":{
"modref":"global.foo_unq1"
}
},
"connections":[
["self.I","foo_inst0.I"],
["foo_inst1.I.0","foo_inst0.O"],
["foo_inst1.I.1","foo_inst0.O"],
["self.O","foo_inst1.O.0"]
]
}
}
}
}
}
52 changes: 52 additions & 0 deletions tests/test_uniquify.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
import magma as m
from magma.testing import check_files_equal


def test_verilog_field_uniquify():
Expand All @@ -11,3 +12,54 @@ def test_verilog_field_uniquify():
assign C = A & B;\
'''
m.EndCircuit()

def test_uniquify_equal():
foo = m.DefineCircuit("foo", "I", m.In(m.Bit), "O", m.Out(m.Bit))
m.wire(foo.I, foo.O)
m.EndCircuit()

bar = m.DefineCircuit("foo", "I", m.In(m.Bit), "O", m.Out(m.Bit))
m.wire(bar.I, bar.O)
m.EndCircuit()

top = m.DefineCircuit("top", "I", m.In(m.Bit), "O", m.Out(m.Bit))
curr = top.I
for circ in (foo, bar):
inst = circ()
m.wire(inst.I, curr)
curr = inst.O
m.wire(curr, top.O)
m.EndCircuit()

assert hash(foo) == hash(bar)

m.compile("build/uniquify_equal", top, output="coreir")
assert check_files_equal(__file__,
"build/uniquify_equal.json",
"gold/uniquify_equal.json")


def test_uniquify_unequal():
foo = m.DefineCircuit("foo", "I", m.In(m.Bit), "O", m.Out(m.Bit))
m.wire(foo.I, foo.O)
m.EndCircuit()

bar = m.DefineCircuit("foo", "I", m.In(m.Bits(2)), "O", m.Out(m.Bits(2)))
m.wire(bar.I, bar.O)
m.EndCircuit()

top = m.DefineCircuit("top", "I", m.In(m.Bit), "O", m.Out(m.Bit))
foo_inst = foo()
m.wire(top.I, foo_inst.I)
bar_inst = bar()
m.wire(foo_inst.O, bar_inst.I[0])
m.wire(foo_inst.O, bar_inst.I[1])
m.wire(bar_inst.O[0], top.O)
m.EndCircuit()

assert hash(foo) != hash(bar)

m.compile("build/uniquify_unequal", top, output="coreir")
assert check_files_equal(__file__,
"build/uniquify_unequal.json",
"gold/uniquify_unequal.json")

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