Merge 77f949b into 2cae041

.gitignore

@@ -99,3 +99,5 @@ parsetab.py
 
 .magma
 .pytest_cache
+build/
+tests/test_verilog/build/

.travis.yml

@@ -12,6 +12,7 @@ before_install:
 install:
 - pip install python-coveralls
 - pip install pytest-cov pytest-pep8
+- pip install -r requirements.txt
 - pip install -e .
 after_success:
 - coveralls

README.md

@@ -102,6 +102,8 @@ $ sudo apt-get install python3 python3-pip
 ## User Setup
 Magma is available as a pip package, install the lastest release with:
 ```
+# Install forked version of pyverilog with basic system verilog support
+pip install git+git://github.com/leonardt/Pyverilog.git#egg=pyverilog
 pip install magma-lang
 ```
 
@@ -114,6 +116,7 @@ $ cd magma
 
 Install magma as a symbolic package
 ```
+$ pip install -r requirements.txt
 $ pip install -e .
 ```
 

magma/compile.py

@@ -140,7 +140,13 @@ def compile(basename, main, output='verilog', **kwargs):
         file_name = basename
 
     if output == 'verilog':
-        write_file(file_name, 'v', verilog.compile(main))
+        suffix = "v"
+        # Handle the case when DefineFromVerilogFile is used with a system
+        # verilog file
+        if hasattr(main, "verilog_file_name") and \
+                os.path.splitext(main.verilog_file_name)[-1] == ".sv":
+            suffix = "sv"
+        write_file(file_name, suffix, verilog.compile(main))
     elif output == 'blif':
         write_file(file_name, 'blif', blif.compile(main))
     elif output == 'firrtl':

magma/fromverilog.py

@@ -152,7 +152,13 @@ def FromVerilogFile(file, func, type_map, target_modules=None):
     if file is None:
         return None
     verilog = open(file).read()
-    return FromVerilog(verilog, func, type_map, target_modules)
+    result = FromVerilog(verilog, func, type_map, target_modules)
+    # Store the original verilog file name, currently used by m.compile to
+    # generate a .sv when compiling a circuit that was defined from a verilog
+    # file
+    for item in result:
+        item.verilog_file_name = file
+    return result
 
 def FromTemplatedVerilog(templatedverilog, func, type_map, **kwargs):
     verilog = Template(templatedverilog).render(**kwargs)

requirements.txt

@@ -0,0 +1 @@
+git+git://github.com/leonardt/Pyverilog.git#egg=pyverilog

setup.py

@@ -23,7 +23,7 @@
         "astor",
         "six",
         "mako",
-        "pyverilog",
+        # "pyverilog",
         "numpy",
         "graphviz",
         "coreir==0.30a0",

tests/test_verilog/test_from_file.py

@@ -21,7 +21,8 @@ def check_rxmod(RXMOD):
 
     m.compile("build/test_rxmod", RXMOD)
     assert m.testing.check_files_equal(__file__, "build/test_rxmod.v",
-            "gold/test_rxmod.v")    
+            "gold/test_rxmod.v")
+
 
 def test_basic():
     file_path = os.path.dirname(__file__)
@@ -71,3 +72,23 @@ def test_decl_list():
         os.path.join(file_path, "decl_list.v"), target_modules=["memory_core"],
         type_map=type_map)[0]
     assert str(memory_core) == "memory_core(clk_in: In(Clock), clk_en: In(Enable), reset: In(AsyncReset), config_addr: In(Bits(32)), config_data: In(Bits(32)), config_read: In(Bit), config_write: In(Bit), config_en: In(Enable), config_en_sram: In(Bits(4)), config_en_linebuf: In(Bit), data_in: In(Bits(16)), data_out: Out(Bits(16)), wen_in: In(Bit), ren_in: In(Bit), valid_out: Out(Bit), chain_in: In(Bits(16)), chain_out: Out(Bits(16)), chain_wen_in: In(Bit), chain_valid_out: Out(Bit), almost_full: Out(Bit), almost_empty: Out(Bit), addr_in: In(Bits(16)), read_data: Out(Bits(32)), read_data_sram: Out(Bits(32)), read_data_linebuf: Out(Bits(32)), flush: In(Bit))"
+
+
+def test_from_sv():
+    file_path = os.path.dirname(__file__)
+    test_pe = m.DefineFromVerilogFile(os.path.join(file_path, "test_pe.sv"))[0]
+
+
+    if os.path.exists("build/test_pe.sv"):
+       os.remove("build/test_pe.sv")
+    m.compile("build/test_pe", test_pe)
+
+    # Remove last line from generated file since magma adds an extra newline
+    with open("tests/test_verilog/build/test_pe.sv", 'r') as f:
+        lines = f.readlines()
+        lines = lines[:-1]
+    with open("tests/test_verilog/build/test_pe.sv", 'w') as f:
+        f.write("".join(lines))
+
+    assert m.testing.check_files_equal(__file__, "build/test_pe.sv",
+                                       "test_pe.sv")