Fix inout in generated verilog

phanrahan · Apr 26, 2019 · 4c771d2 · 4c771d2
1 parent c162227
commit 4c771d2
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/tests/test_verilog/gold/test_pad.v b/tests/test_verilog/gold/test_pad.v
@@ -14,7 +14,7 @@ module PRWDWUWSWCDGH_V (
   input  I,
   input  IE,
   input  OEN,
-  output  PAD,
+  inout  PAD,
   input  PD,
   input  PU,
   input  RTE,
@@ -26,7 +26,7 @@ endmodule  // PRWDWUWSWCDGH_V
 
 */
 module Top (
-  output  pad
+  inout  pad
 );
 
 

diff --git a/tests/test_verilog/test_from_file.py b/tests/test_verilog/test_from_file.py
@@ -94,7 +94,7 @@ def test_from_sv():
                                        "test_pe.sv")
 
 
-def test_from_pad_out():
+def test_from_pad_inout():
     file_path = os.path.dirname(__file__)
     Pad = m.DeclareFromVerilogFile(os.path.join(file_path, "pad.v"))[0]