Merge e787753 into f4ae6ca

magma/backend/coreir_.py

@@ -268,7 +268,7 @@ def compile_definition_to_module_definition(self, definition, module_definition)
             wiredefaultclock(definition, instance)
             wireclock(definition, instance)
             coreir_instance = self.compile_instance(instance, module_definition)
-            if get_codegen_debug_info() and instance.debug_info:
+            if get_codegen_debug_info() and getattr(instance, "debug_info", False):
                 coreir_instance.add_metadata("filename", json.dumps(make_relative(instance.debug_info.filename)))
                 coreir_instance.add_metadata("lineno", json.dumps(str(instance.debug_info.lineno)))
             for name, port in instance.interface.ports.items():
@@ -364,7 +364,7 @@ def is_clock_or_nested_clock(p):
             source = module_definition.select(non_input_ports[value])
         sink = module_definition.select(magma_port_to_coreir(port))
         module_definition.connect(source, sink)
-        if get_codegen_debug_info() and hasattr(port, "debug_info"):
+        if get_codegen_debug_info() and getattr(port, "debug_info", False):
             module_definition.add_metadata(source, sink, "filename", json.dumps(make_relative(port.debug_info.filename)))
             module_definition.add_metadata(source, sink, "lineno", json.dumps(str(port.debug_info.lineno)))
 

magma/backend/verilog.py

@@ -113,7 +113,7 @@ def arg(k,v):
     args = []
     debug_str = ""
     for k, v in self.interface.ports.items():
-        if hasattr(v, "debug_info") and get_codegen_debug_info():
+        if getattr(v, "debug_info", False) and get_codegen_debug_info():
             filename, lineno, module = v.debug_info
         #print('arg', k, v,)
         if v.isinput():
@@ -131,7 +131,7 @@ def arg(k,v):
             args.append( vname(v) )
         else:
             args.append( arg(k,vname(v)) )
-        if hasattr(v, "debug_info") and get_codegen_debug_info():
+        if getattr(v, "debug_info", False) and get_codegen_debug_info():
             debug_str += f"// Argument {k}({vname(v)}) wired at {make_relative(filename)}:{lineno}\n"
 
     params = []
@@ -199,7 +199,9 @@ def wire(port):
             # emit the structured verilog for each instance
             for instance in cls.instances:
                 wiredefaultclock(cls, instance)
-                if instance.debug_info.filename and instance.debug_info.lineno and get_codegen_debug_info():
+                if getattr(instance, "debug_info", False) and \
+                        instance.debug_info.filename and instance.debug_info.lineno and \
+                        get_codegen_debug_info():
                     s += f"// Instanced at {make_relative(instance.debug_info.filename)}:{instance.debug_info.lineno}\n"
                 s += compileinstance(instance) + ";\n"
 
@@ -220,7 +222,7 @@ def wire(port):
                         else:
                             iname = vname(port)
                             oname = vname(output)
-                            if hasattr(port, "debug_info") and get_codegen_debug_info():
+                            if getattr(port, "debug_info", False) and get_codegen_debug_info():
                                 s += f"// Wired at {make_relative(port.debug_info[0])}:{port.debug_info[1]}\n"
                             s += 'assign %s = %s;\n' % (iname, oname)
                     else:

magma/circuit.py

@@ -13,6 +13,7 @@
 from .array import ArrayType
 from .tuple import TupleType
 from .bit import VCC, GND
+from .config import get_debug_mode
 from .debug import get_callee_frame_info, debug_info
 from .logging import warning
 from .port import report_wiring_warning
@@ -73,11 +74,15 @@ def __new__(metacls, name, bases, dct):
 
         if 'coreir_lib' not in dct:
             dct['coreir_lib'] = "global"
-        if "debug_info" not in dct:
-            callee_frame = inspect.getframeinfo(inspect.currentframe().f_back.f_back)
-            module = inspect.getmodule(inspect.stack()[2][0])
-            dct["debug_info"] = debug_info(callee_frame.filename,
-                                           callee_frame.lineno, module)
+        if get_debug_mode():
+            if not dct.get("debug_info", False):
+                callee_frame = inspect.getframeinfo(inspect.currentframe().f_back.f_back)
+                module = inspect.getmodule(inspect.stack()[2][0])
+                dct["debug_info"] = debug_info(callee_frame.filename,
+                                               callee_frame.lineno, module)
+        else:
+            dct["debug_info"] = None
+
 
         # create a new circuit class
         cls = type.__new__(metacls, name, bases, dct)
@@ -95,9 +100,10 @@ def __new__(metacls, name, bases, dct):
 
     def __call__(cls, *largs, **kwargs):
         #print('CircuitKind call:', largs, kwargs)
-        debug_info = get_callee_frame_info()
         self = super(CircuitKind, cls).__call__(*largs, **kwargs)
-        self.set_debug_info(debug_info)
+        if get_debug_mode():
+            debug_info = get_callee_frame_info()
+            self.set_debug_info(debug_info)
 
         # instance interface for this instance
         if hasattr(cls, 'IO'):
@@ -262,7 +268,10 @@ def debug_name(self):
         return f"{defn_str}.{self.name}"
 
     def __call__(input, *outputs, **kw):
-        debug_info = get_callee_frame_info()
+        if get_debug_mode():
+            debug_info = get_callee_frame_info()
+        else:
+            debug_info = None
 
         no = len(outputs)
         if len(outputs) == 1:
@@ -364,7 +373,10 @@ def __repr__(self):
 
 # DeclareCircuit Factory
 def DeclareCircuit(name, *decl, **args):
-    debug_info = get_callee_frame_info()
+    if get_debug_mode():
+        debug_info = get_callee_frame_info()
+    else:
+        debug_info = None
     dct = dict(
         IO=decl,
         debug_info=debug_info,
@@ -475,7 +487,8 @@ def place(cls, inst):
             inst.name = f"{type(inst).name}_inst{str(cls.instanced_circuits_counter[type(inst).name])}"
             cls.instanced_circuits_counter[type(inst).name] += 1
         inst.defn = cls
-        inst.stack = inspect.stack()
+        if get_debug_mode():
+            inst.stack = inspect.stack()
         cls.instances.append(inst)
 
 
@@ -499,7 +512,10 @@ class Circuit(CircuitType):
 
 # DefineCircuit Factory
 def DefineCircuit(name, *decl, **args):
-    debug_info = get_callee_frame_info()
+    if get_debug_mode():
+        debug_info = get_callee_frame_info()
+    else:
+        debug_info = None
     global currentDefinition
     if currentDefinition:
         currentDefinitionStack.append(currentDefinition)

magma/compile.py

@@ -25,7 +25,7 @@ def __init__(self, main):
         self.has_mantle_circuit = False
 
     def __call__(self, definition):
-        if definition.debug_info.module is not None and \
+        if getattr(definition, "debug_info", False) and \
                 definition.debug_info.module.__name__.split(".")[0] == "mantle":
             self.has_mantle_circuit = True
 

magma/config.py

@@ -9,3 +9,16 @@ def set_compile_dir(target):
 
 def get_compile_dir():
     return __COMPILE_DIR
+
+
+__DEBUG_MODE = False
+
+
+def set_debug_mode(value=True):
+    global __DEBUG_MODE
+    assert value in {True, False}
+    __DEBUG_MODE = value
+
+
+def get_debug_mode():
+    return __DEBUG_MODE

magma/debug.py

@@ -1,6 +1,7 @@
 import inspect
 import collections
 import magma
+from magma.config import get_debug_mode
 
 
 debug_info = collections.namedtuple("debug_info", ["filename", "lineno", "module"])
@@ -28,7 +29,7 @@ def debug_wire(fn):
     # TODO: We could check that fn has the correct interface
     #       wire(i, o, debug_info)
     def wire(i, o, debug_info=None):
-        if debug_info is None:
+        if get_debug_mode() and debug_info is None:
             debug_info = get_callee_frame_info()
         return fn(i, o, debug_info)
     return wire

magma/port.py

@@ -12,21 +12,27 @@
 
 
 def report_wiring_error(message, debug_info):
-    error(f"\033[1m{make_relative(debug_info[0])}:{debug_info[1]}: {message}",
-          include_wire_traceback=True)
-    try:
-        error(get_source_line(debug_info[0], debug_info[1]))
-    except FileNotFoundError:
-        error(f"    Could not find file {debug_info[0]}")
+    if debug_info:
+        error(f"\033[1m{make_relative(debug_info[0])}:{debug_info[1]}: {message}",
+              include_wire_traceback=True)
+        try:
+            error(get_source_line(debug_info[0], debug_info[1]))
+        except FileNotFoundError:
+            error(f"    Could not find file {debug_info[0]}")
+    else:
+        error(message)
 
 
 def report_wiring_warning(message, debug_info):
     # TODO: Include wire traceback support
-    warning(f"\033[1m{make_relative(debug_info[0])}:{debug_info[1]}: {message}")
-    try:
-        warning(get_source_line(debug_info[0], debug_info[1]))
-    except FileNotFoundError:
-        warning(f"    Could not find file {debug_info[0]}")
+    if debug_info:
+        warning(f"\033[1m{make_relative(debug_info[0])}:{debug_info[1]}: {message}")
+        try:
+            warning(get_source_line(debug_info[0], debug_info[1]))
+        except FileNotFoundError:
+            warning(f"    Could not find file {debug_info[0]}")
+    else:
+        warning(message)
 
 
 def flip(direction):

magma/syntax/combinational.py

@@ -12,6 +12,7 @@
 import types
 from magma.debug import debug_info
 from magma.ssa import convert_tree_to_ssa
+from magma.config import get_debug_mode
 
 
 class CircuitDefinitionSyntaxError(Exception):
@@ -213,9 +214,10 @@ def combinational(defn_env: dict, fn: types.FunctionType):
     debug(source)
     circuit_def = ast_utils.compile_function_to_file(tree, fn.__name__,
                                                      defn_env)
-    circuit_def.debug_info = debug_info(circuit_def.debug_info.filename,
-                                        circuit_def.debug_info.lineno,
-                                        inspect.getmodule(fn))
+    if get_debug_mode() and getattr(circuit_def, "debug_info", False):
+        circuit_def.debug_info = debug_info(circuit_def.debug_info.filename,
+                                            circuit_def.debug_info.lineno,
+                                            inspect.getmodule(fn))
 
     @functools.wraps(fn)
     def func(*args, **kwargs):

magma/syntax/sequential.py

@@ -7,6 +7,7 @@
 import functools
 import magma as m
 from magma.ssa import convert_tree_to_ssa
+from magma.config import get_debug_mode
 from collections import Counter
 
 
@@ -355,9 +356,10 @@ def _sequential(defn_env: dict, cls):
             ast.parse("from mantle import DefineRegister").body[0],
         ] + tree.body)
     circuit_def = ast_utils.compile_function_to_file(tree, cls.__name__, defn_env)
-    circuit_def.debug_info = debug_info(circuit_def.debug_info.filename,
-                                        circuit_def.debug_info.lineno,
-                                        inspect.getmodule(cls))
+    if get_debug_mode() and getattr(circuit_def, "debug_info", False):
+        circuit_def.debug_info = debug_info(circuit_def.debug_info.filename,
+                                            circuit_def.debug_info.lineno,
+                                            inspect.getmodule(cls))
 
     return circuit_def
 

tests/test_circuit/gold/test_for_loop_def.json

@@ -8,7 +8,7 @@
           ["I1","BitIn"],
           ["O","Bit"]
         ]],
-        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"53"}
+        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"54"}
       },
       "main":{
         "type":["Record",[
@@ -18,33 +18,33 @@
         "instances":{
           "And2_inst0":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"59"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           },
           "And2_inst1":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"59"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           },
           "And2_inst2":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"59"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           },
           "And2_inst3":{
             "modref":"global.And2",
-            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"59"}
+            "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"60"}
           }
         },
         "connections":[
-          ["self.I.0","And2_inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
-          ["self.I.1","And2_inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
-          ["And2_inst1.I0","And2_inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"64"}],
-          ["self.I.1","And2_inst1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
-          ["And2_inst2.I0","And2_inst1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"64"}],
-          ["self.I.1","And2_inst2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
-          ["And2_inst3.I0","And2_inst2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"64"}],
-          ["self.I.1","And2_inst3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
-          ["self.O","And2_inst3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"68"}]
+          ["self.I.0","And2_inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
+          ["self.I.1","And2_inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"63"}],
+          ["And2_inst1.I0","And2_inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
+          ["self.I.1","And2_inst1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
+          ["And2_inst2.I0","And2_inst1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
+          ["self.I.1","And2_inst2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
+          ["And2_inst3.I0","And2_inst2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}],
+          ["self.I.1","And2_inst3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}],
+          ["self.O","And2_inst3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"69"}]
         ],
-        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"55"}
+        "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"}
       }
     }
   }

tests/test_circuit/gold/test_for_loop_def.v

@@ -1,30 +1,30 @@
-// Defined at tests/test_circuit/test_define.py:55
+// Defined at tests/test_circuit/test_define.py:56
 module main (input [1:0] I, output  O);
 wire  And2_inst0_O;
 wire  And2_inst1_O;
 wire  And2_inst2_O;
 wire  And2_inst3_O;
-// Instanced at tests/test_circuit/test_define.py:59
-// Argument I0(I[0]) wired at tests/test_circuit/test_define.py:61
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:62
-// Argument O(And2_inst0_O) wired at tests/test_circuit/test_define.py:64
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(I[0]) wired at tests/test_circuit/test_define.py:62
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:63
+// Argument O(And2_inst0_O) wired at tests/test_circuit/test_define.py:65
 And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
-// Instanced at tests/test_circuit/test_define.py:59
-// Argument I0(And2_inst0_O) wired at tests/test_circuit/test_define.py:64
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:65
-// Argument O(And2_inst1_O) wired at tests/test_circuit/test_define.py:64
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(And2_inst0_O) wired at tests/test_circuit/test_define.py:65
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:66
+// Argument O(And2_inst1_O) wired at tests/test_circuit/test_define.py:65
 And2 And2_inst1 (.I0(And2_inst0_O), .I1(I[1]), .O(And2_inst1_O));
-// Instanced at tests/test_circuit/test_define.py:59
-// Argument I0(And2_inst1_O) wired at tests/test_circuit/test_define.py:64
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:65
-// Argument O(And2_inst2_O) wired at tests/test_circuit/test_define.py:64
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(And2_inst1_O) wired at tests/test_circuit/test_define.py:65
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:66
+// Argument O(And2_inst2_O) wired at tests/test_circuit/test_define.py:65
 And2 And2_inst2 (.I0(And2_inst1_O), .I1(I[1]), .O(And2_inst2_O));
-// Instanced at tests/test_circuit/test_define.py:59
-// Argument I0(And2_inst2_O) wired at tests/test_circuit/test_define.py:64
-// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:65
-// Argument O(And2_inst3_O) wired at tests/test_circuit/test_define.py:68
+// Instanced at tests/test_circuit/test_define.py:60
+// Argument I0(And2_inst2_O) wired at tests/test_circuit/test_define.py:65
+// Argument I1(I[1]) wired at tests/test_circuit/test_define.py:66
+// Argument O(And2_inst3_O) wired at tests/test_circuit/test_define.py:69
 And2 And2_inst3 (.I0(And2_inst2_O), .I1(I[1]), .O(And2_inst3_O));
-// Wired at tests/test_circuit/test_define.py:68
+// Wired at tests/test_circuit/test_define.py:69
 assign O = And2_inst3_O;
 endmodule