Fixed InOut test.

phanrahan · Aug 8, 2018 · 6d8f397 · 6d8f397
1 parent b937d1d
commit 6d8f397
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/tests/test_verilog/test_simple.py b/tests/test_verilog/test_simple.py
@@ -12,7 +12,7 @@ def test_simple():
     v = DeclareFromVerilog(s)
     top = v[0]
     assert top.name == "top"
-    assert repr(top.IO) == "Interface(a, In(Bit), b, Out(Bit), c, Bit)"
+    assert repr(top.IO) == "Interface(a, In(Bit), b, Out(Bit), c, InOut(Bit))"
 
 def test_small():
     file_path = os.path.dirname(__file__)