Revert "Swap isinput isoutput logic"

This reverts commit 0e56762.

magma/testing/verilator.py

@@ -73,7 +73,7 @@ def regression_harness(circuit,tests):
 
 def harness(circuit,tests):
 
-    assert len(circuit.interface.ports.keys()) == len(tests[0]), (len(circuit.interface.ports.keys()), len(tests[0]))
+    assert len(circuit.interface.ports.keys()) == len(tests[0])
 
     source = '''\
 #include "V{name}.h"
@@ -94,7 +94,7 @@ def harness(circuit,tests):
         testvector = ', '.join([t.as_binary_string() for t in test])
         #testvector += ', {}'.format(int(func(*test[:nargs])))
         source += '''\
-        {{ {} }},
+        {{ {} }}, 
 '''.format(testvector)
     source += '''\
     };
@@ -107,7 +107,7 @@ def harness(circuit,tests):
 
     i = 0
     for name, port in circuit.interface.ports.items():
-        if port.isinput():
+        if port.isoutput():
             source += '''\
         top->{} = test[{}];
 '''.format(name,i)
@@ -119,7 +119,7 @@ def harness(circuit,tests):
 
     i = 0
     for name, port in circuit.interface.ports.items():
-        if port.isoutput():
+        if port.isinput():
             source += '''\
         assert(top->{} == test[{}]);
 '''.format(name,i)