Merge 10f2007 into 995e08d

.magma/basic_func.py

@@ -0,0 +1,7 @@
+class basic_func(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'S', m.In(m.Bit), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = mux([io.I[1], io.I[0]], io.S)
+        m.wire(O, io.O)

.magma/basic_function_call.py

@@ -0,0 +1,7 @@
+class basic_function_call(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'S', m.In(m.Bit), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = basic_func(io.I, io.S)
+        m.wire(O, io.O)

.magma/basic_if.py

@@ -0,0 +1,7 @@
+class basic_if(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'S', m.In(m.Bit), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = mux([io.I[1], io.I[0]], io.S)
+        m.wire(O, io.O)

.magma/if_statement_nested.py

@@ -0,0 +1,8 @@
+class if_statement_nested(m.Circuit):
+    IO = ['I', m.In(m.Bits(4)), 'S', m.In(m.Bits(2)), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = mux([mux([io.I[3], io.I[2]], io.S[1]), mux([io.I[1], io.I[0]],
+            io.S[1])], io.S[0])
+        m.wire(O, io.O)

.magma/logic.py

@@ -0,0 +1,9 @@
+class logic(m.Circuit):
+    IO = ['a', m.In(m.Bit), 'O0', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        c = mux([m.bit(1), mux([m.bit(0), m.bit(0)], EQ()(io.a, m.bit(0)))],
+            EQ()(io.a, m.bit(0)))
+        O0, = c,
+        m.wire(O0, io.O0)

.magma/return_magma_named_tuple.py

@@ -0,0 +1,7 @@
+class return_magma_named_tuple(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'O', m.Out(m.Tuple(x=m.Bit, y=m.Bit))]
+
+    @classmethod
+    def definition(io):
+        O = m.namedtuple(x=io.I[0], y=io.I[1])
+        m.wire(O, io.O)

.magma/return_magma_tuple.py

@@ -0,0 +1,7 @@
+class return_magma_tuple(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'O', m.Out(m.Tuple(m.Bit, m.Bit))]
+
+    @classmethod
+    def definition(io):
+        O = m.tuple_([io.I[0], io.I[1]])
+        m.wire(O, io.O)

.magma/return_py_tuple.py

@@ -0,0 +1,8 @@
+class return_py_tuple(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'O0', m.Out(m.Bit), 'O1', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O0, O1 = io.I[0], io.I[1]
+        m.wire(O0, io.O0)
+        m.wire(O1, io.O1)

.magma/ternary.py

@@ -0,0 +1,7 @@
+class ternary(m.Circuit):
+    IO = ['I', m.In(m.Bits(2)), 'S', m.In(m.Bit), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = mux([io.I[1], io.I[0]], io.S)
+        m.wire(O, io.O)

.magma/ternary_nested.py

@@ -0,0 +1,7 @@
+class ternary_nested(m.Circuit):
+    IO = ['I', m.In(m.Bits(4)), 'S', m.In(m.Bits(2)), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = mux([mux([io.I[2], io.I[1]], io.S[1]), io.I[0]], io.S[0])
+        m.wire(O, io.O)

.magma/ternary_nested2.py

@@ -0,0 +1,7 @@
+class ternary_nested2(m.Circuit):
+    IO = ['I', m.In(m.Bits(4)), 'S', m.In(m.Bits(2)), 'O', m.Out(m.Bit)]
+
+    @classmethod
+    def definition(io):
+        O = mux([io.I[2], mux([io.I[1], io.I[0]], io.S[0])], io.S[1])
+        m.wire(O, io.O)

.magma/txmod_logic.py

@@ -0,0 +1,51 @@
+from mantle import mux
+import magma as m
+
+
+class txmod_logic(m.Circuit):
+    IO = ['data', m.In(m.Bits(8)), 'writing', m.In(m.Bit), 'valid', m.In(m.
+        Bit), 'dataStore', m.In(m.Bits(11)), 'writeClock', m.In(m.Bits(14)),
+        'writeBit', m.In(m.Bits(4)), 'O0', m.Out(m.Bit), 'O1', m.Out(m.Bits
+        (11)), 'O2', m.Out(m.Bits(14)), 'O3', m.Out(m.Bits(4)), 'O4', m.Out
+        (m.Bit)]
+
+    @classmethod
+    def definition(io):
+        writing_out = mux([mux([mux([mux([io.writing, io.writing], io.
+            writing == m.bit(1)), io.writing], (io.writing == m.bit(1)) & (
+            io.writeClock == m.bits(0, 14))), m.bit(0)], (io.writing == m.
+            bit(1)) & (io.writeClock == m.bits(0, 14)) & (io.writeBit == m.
+            bits(9, 4))), m.bit(1)], (io.writing == m.bit(0)) & (io.valid ==
+            m.bit(0)))
+        dataStore_out = mux([mux([mux([mux([io.dataStore, io.dataStore], io
+            .writing == m.bit(1)), io.dataStore], (io.writing == m.bit(1)) &
+            (io.writeClock == m.bits(0, 14))), io.dataStore], (io.writing ==
+            m.bit(1)) & (io.writeClock == m.bits(0, 14)) & (io.writeBit ==
+            m.bits(9, 4))), m.concat(io.dataStore[0:1], io.data, io.
+            dataStore[9:])], (io.writing == m.bit(0)) & (io.valid == m.bit(0)))
+        writeClock_out = mux([mux([mux([mux([io.writeClock, m.bits(m.uint(
+            io.writeClock) - m.bits(1, 14))], io.writing == m.bit(1)), m.
+            bits(100, 14)], (io.writing == m.bit(1)) & (io.writeClock == m.
+            bits(0, 14))), io.writeClock], (io.writing == m.bit(1)) & (io.
+            writeClock == m.bits(0, 14)) & (io.writeBit == m.bits(9, 4))),
+            m.bits(100, 14)], (io.writing == m.bit(0)) & (io.valid == m.bit(0))
+            )
+        writeBit_out = mux([mux([mux([mux([io.writeBit, io.writeBit], io.
+            writing == m.bit(1)), m.bits(m.uint(io.writeBit) + m.bits(1, 4)
+            )], (io.writing == m.bit(1)) & (io.writeClock == m.bits(0, 14))
+            ), io.writeBit], (io.writing == m.bit(1)) & (io.writeClock == m
+            .bits(0, 14)) & (io.writeBit == m.bits(9, 4))), m.bits(0, 4)], 
+            (io.writing == m.bit(0)) & (io.valid == m.bit(0)))
+        TXReg_out = mux([mux([mux([mux([m.bit(1), io.dataStore[io.writeBit]
+            ], io.writing == m.bit(1)), io.dataStore[io.writeBit]], (io.
+            writing == m.bit(1)) & (io.writeClock == m.bits(0, 14))), m.bit
+            (1)], (io.writing == m.bit(1)) & (io.writeClock == m.bits(0, 14
+            )) & (io.writeBit == m.bits(9, 4))), io.dataStore[0]], (io.
+            writing == m.bit(0)) & (io.valid == m.bit(0)))
+        O0, O1, O2, O3, O4 = (writing_out, dataStore_out, writeClock_out,
+            writeBit_out, TXReg_out)
+        m.wire(O0, io.O0)
+        m.wire(O1, io.O1)
+        m.wire(O2, io.O2)
+        m.wire(O3, io.O3)
+        m.wire(O4, io.O4)

.pytest_cache/README.md

@@ -0,0 +1,8 @@
+# pytest cache directory #
+
+This directory contains data from the pytest's cache plugin,
+which provides the `--lf` and `--ff` options, as well as the `cache` fixture.
+
+**Do not** commit this to version control.
+
+See [the docs](https://docs.pytest.org/en/latest/cache.html) for more information.

.pytest_cache/v/cache/lastfailed

@@ -0,0 +1,5 @@
+{
+  "tests/test_circuit_def.py::test_source_file_error": true,
+  "tests/test_debug_info.py::test_filename_lineno_verilog": true,
+  "tests/test_wire/test_errors.py::test_multiple_outputs_to_input_error": true
+}

.pytest_cache/v/cache/nodeids

@@ -0,0 +1,150 @@
+[
+  "tests/test_circuit_def.py::test_if_statement_basic[verilog]",
+  "tests/test_circuit_def.py::test_if_statement_basic[coreir]",
+  "tests/test_circuit_def.py::test_if_statement_nested[verilog]",
+  "tests/test_circuit_def.py::test_if_statement_nested[coreir]",
+  "tests/test_circuit_def.py::test_ternary[verilog]",
+  "tests/test_circuit_def.py::test_ternary[coreir]",
+  "tests/test_circuit_def.py::test_ternary_nested[verilog]",
+  "tests/test_circuit_def.py::test_ternary_nested[coreir]",
+  "tests/test_circuit_def.py::test_ternary_nested2[verilog]",
+  "tests/test_circuit_def.py::test_ternary_nested2[coreir]",
+  "tests/test_circuit_def.py::test_function_composition[verilog]",
+  "tests/test_circuit_def.py::test_function_composition[coreir]",
+  "tests/test_circuit_def.py::test_return_py_tuple[verilog]",
+  "tests/test_circuit_def.py::test_return_py_tuple[coreir]",
+  "tests/test_circuit_def.py::test_return_magma_tuple[verilog]",
+  "tests/test_circuit_def.py::test_return_magma_tuple[coreir]",
+  "tests/test_circuit_def.py::test_return_magma_named_tuple[verilog]",
+  "tests/test_circuit_def.py::test_return_magma_named_tuple[coreir]",
+  "tests/test_circuit_def.py::test_simple_circuit_1[verilog]",
+  "tests/test_circuit_def.py::test_simple_circuit_1[coreir]",
+  "tests/test_circuit_def.py::test_warnings",
+  "tests/test_circuit_def.py::test_not_implemented",
+  "tests/test_compile_errors.py::test_multiple_definitions_are_same",
+  "tests/test_compile_errors.py::test_multiple_definitions_are_same_older_def_approach",
+  "tests/test_compile_errors.py::test_same_definitions",
+  "tests/test_flatten.py::test_flatten",
+  "tests/test_operators.py::test_error",
+  "tests/test_circuit/test_circuit_generator.py::test_add_generator",
+  "tests/test_circuit/test_define.py::test_simple_def",
+  "tests/test_circuit/test_define.py::test_unwired_ports_warnings",
+  "tests/test_circuit/test_define.py::test_2d_array_error",
+  "tests/test_circuit/test_is_definition.py::test_is_definition",
+  "tests/test_circuit/test_is_definition.py::test_is_not_definition",
+  "tests/test_coreir/test_coreir.py::test_check_interface_bit",
+  "tests/test_coreir/test_coreir.py::test_check_interface_array",
+  "tests/test_coreir/test_coreir.py::test_check_interface_tuple",
+  "tests/test_coreir/test_coreir.py::test_nested_clocks",
+  "tests/test_coreir/test_coreir_compile.py::test_compile_coreir",
+  "tests/test_coreir/test_linking.py::test_declare_generator",
+  "tests/test_dot/test_dot.py::test",
+  "tests/test_higher/test_braid.py::test_braid",
+  "tests/test_higher/test_braid.py::test_compose",
+  "tests/test_higher/test_curry.py::test_lut",
+  "tests/test_higher/test_curry.py::test_rom",
+  "tests/test_higher/test_flat.py::test_flat",
+  "tests/test_higher/test_flat.py::test_partition",
+  "tests/test_higher/test_fork.py::test",
+  "tests/test_higher/test_join.py::test",
+  "tests/test_interface/test_interface.py::test_1",
+  "tests/test_io/test_inout1.py::test",
+  "tests/test_io/test_inout2.py::test",
+  "tests/test_io/test_out1.py::test",
+  "tests/test_io/test_out2.py::test",
+  "tests/test_ir/test_declaretest.py::test",
+  "tests/test_ir/test_ir.py::test_print_ir",
+  "tests/test_meta/test_class.py::test",
+  "tests/test_meta/test_creg.py::test",
+  "tests/test_simulator/test_counter.py::test",
+  "tests/test_simulator/test_error.py::test_instance",
+  "tests/test_simulator/test_ff.py::test",
+  "tests/test_simulator/test_logic.py::test",
+  "tests/test_simulator/test_mdb.py::test",
+  "tests/test_simulator/test_nested.py::test_simulator_nested_simple",
+  "tests/test_simulator/test_nested.py::test_simulator_nested_complex",
+  "tests/test_simulator/test_tuple.py::test_simulator_tuple",
+  "tests/test_type/test_anon.py::test",
+  "tests/test_type/test_array.py::test",
+  "tests/test_type/test_array.py::test_val",
+  "tests/test_type/test_array.py::test_flip",
+  "tests/test_type/test_array.py::test_array2d",
+  "tests/test_type/test_array.py::test_construct",
+  "tests/test_type/test_array.py::test_whole",
+  "tests/test_type/test_array.py::test_wire",
+  "tests/test_type/test_bit.py::test_bit",
+  "tests/test_type/test_bit.py::test_bit_flip",
+  "tests/test_type/test_bit.py::test_bit_val",
+  "tests/test_type/test_bit.py::test_vcc",
+  "tests/test_type/test_bit.py::test_wire1",
+  "tests/test_type/test_bit.py::test_wire2",
+  "tests/test_type/test_bit.py::test_wire3",
+  "tests/test_type/test_bit.py::test_wire4",
+  "tests/test_type/test_bit.py::test_wire5",
+  "tests/test_type/test_bits.py::test",
+  "tests/test_type/test_bits.py::test_val",
+  "tests/test_type/test_bits.py::test_flip",
+  "tests/test_type/test_bits.py::test_construct",
+  "tests/test_type/test_clock.py::test_clock",
+  "tests/test_type/test_clock.py::test_clock_flip",
+  "tests/test_type/test_clock.py::test_clock_val",
+  "tests/test_type/test_clock.py::test_reset",
+  "tests/test_type/test_clock.py::test_reset_flip",
+  "tests/test_type/test_clock.py::test_reset_val",
+  "tests/test_type/test_clock.py::test_enable",
+  "tests/test_type/test_clock.py::test_enable_flip",
+  "tests/test_type/test_clock.py::test_enable_val",
+  "tests/test_type/test_conversions.py::test_bit",
+  "tests/test_type/test_conversions.py::test_enable",
+  "tests/test_type/test_conversions.py::test_reset",
+  "tests/test_type/test_conversions.py::test_clock",
+  "tests/test_type/test_conversions.py::test_array",
+  "tests/test_type/test_conversions.py::test_bits",
+  "tests/test_type/test_conversions.py::test_uint",
+  "tests/test_type/test_conversions.py::test_sint",
+  "tests/test_type/test_conversions.py::test_tuple",
+  "tests/test_type/test_sint.py::test",
+  "tests/test_type/test_sint.py::test_val",
+  "tests/test_type/test_sint.py::test_flip",
+  "tests/test_type/test_sint.py::test_construct",
+  "tests/test_type/test_tuple.py::test_pair",
+  "tests/test_type/test_tuple.py::test_dict",
+  "tests/test_type/test_tuple.py::test_flip",
+  "tests/test_type/test_tuple.py::test_wire",
+  "tests/test_type/test_tuple.py::test_val",
+  "tests/test_type/test_type_errors.py::test_array_lengths",
+  "tests/test_type/test_type_errors.py::test_array_to_bit",
+  "tests/test_type/test_type_errors.py::test_tuple_to_array",
+  "tests/test_type/test_type_errors.py::test_bad_tuples",
+  "tests/test_type/test_type_errors.py::test_bit_to_array",
+  "tests/test_type/test_uint.py::test",
+  "tests/test_type/test_uint.py::test_val",
+  "tests/test_type/test_uint.py::test_flip",
+  "tests/test_type/test_uint.py::test_construct",
+  "tests/test_verilog/test_from_file.py::test",
+  "tests/test_verilog/test_simple.py::test_simple",
+  "tests/test_verilog/test_simple.py::test_small",
+  "tests/test_wire/test_arg.py::test_arg1",
+  "tests/test_wire/test_arg.py::test_arg2",
+  "tests/test_wire/test_arg.py::test_pos",
+  "tests/test_wire/test_arg.py::test_arg_array1",
+  "tests/test_wire/test_arg.py::test_arg_array2",
+  "tests/test_wire/test_arg.py::test_arg_array3",
+  "tests/test_wire/test_call.py::test_call1",
+  "tests/test_wire/test_call.py::test_call2",
+  "tests/test_wire/test_compose.py::test",
+  "tests/test_wire/test_const.py::test_const0",
+  "tests/test_wire/test_const.py::test_const1",
+  "tests/test_wire/test_errors.py::test_input_as_output",
+  "tests/test_wire/test_errors.py::test_output_as_input",
+  "tests/test_wire/test_errors.py::test_multiple_outputs_to_input_warning",
+  "tests/test_wire/test_errors.py::test_muliple_outputs_circuit",
+  "tests/test_wire/test_errors.py::test_no_inputs_circuit",
+  "tests/test_wire/test_errors.py::test_muliple_inputs_circuit",
+  "tests/test_wire/test_errors.py::test_no_key",
+  "tests/test_wire/test_flip.py::test_flip",
+  "tests/test_wire/test_named.py::test_named1",
+  "tests/test_wire/test_named.py::test_named2",
+  "tests/test_wire/test_named.py::test_named3",
+  "tests/test_wire/test_named.py::test_named4"
+]

magma/__init__.py

@@ -55,3 +55,5 @@ def set_mantle_target(t):
      if mantle_target is not None and mantle_target != t:
          warning('changing mantle target', mantle_target, t )
      mantle_target = t
+
+from .backend.util import set_codegen_debug_info

magma/backend/coreir_.py

@@ -13,6 +13,8 @@
 from ..passes import InstanceGraphPass
 from ..t import In
 import logging
+from .util import make_relative, get_codegen_debug_info
+from ..interface import InterfaceKind
 
 from collections import defaultdict
 
@@ -227,7 +229,11 @@ def compile_declaration(self, declaration):
         if declaration.coreir_lib in ["coreir", "corebit", "commonlib"]:
             return
         module_type = self.convert_interface_to_module_type(declaration.interface)
-        coreir_module = self.context.global_namespace.new_module(declaration.coreir_name, module_type)
+        if isinstance(declaration.interface, InterfaceKind):
+            module_type = self.context.Flip(module_type)
+
+        coreir_module = self.context.global_namespace.new_module(declaration.coreir_name,
+                                                                 module_type)
 
     def compile_definition_to_module_definition(self, definition, module_definition):
         output_ports = {}
@@ -239,6 +245,9 @@ def compile_definition_to_module_definition(self, definition, module_definition)
             wiredefaultclock(definition, instance)
             wireclock(definition, instance)
             coreir_instance = self.compile_instance(instance, module_definition)
+            if get_codegen_debug_info() and instance.filename and instance.lineno:
+                coreir_instance.add_metadata("filename", make_relative(instance.filename))
+                coreir_instance.add_metadata("lineno", str(instance.lineno))
             for name, port in instance.interface.ports.items():
                 if port.isoutput():
                     self.add_output_port(output_ports, port)

magma/backend/verilog.py

@@ -24,14 +24,7 @@
     logging.warning("Unsupported value for MAGMA_VERILOG_BACKEND_LOG_LEVEL:"
                     f" {level}")
 
-
-def get_codegen_debug_info():
-    return os.environ.get('MAGMA_CODEGEN_DEBUG_INFO', False)
-
-def make_relative(path):
-    cwd = os.getcwd()
-    common_prefix = os.path.commonprefix([cwd, path])
-    return os.path.relpath(path, common_prefix)
+from .util import get_codegen_debug_info, make_relative
 
 coreir_primitives_file_path = os.path.join(
     os.path.dirname(os.path.realpath(__file__)), "coreir_prims.v")