Update from verilog tests

phanrahan · Oct 19, 2018 · 85a57ba · 85a57ba
1 parent 8597657
commit 85a57ba
Showing 1 changed file with 13 additions and 14 deletions.
diff --git a/tests/test_verilog/test_from_file.py b/tests/test_verilog/test_from_file.py
@@ -13,28 +13,27 @@ def check_port(definition, port, type, direction):
     else:
         raise NotImplementedError(direction)
 
-def test():
-    file_path = os.path.dirname(__file__)
-    RXMOD = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"))[0]
-
+def check_rxmod(RXMOD):
     check_port(RXMOD, "RX", m.BitType, "input")
     check_port(RXMOD, "CLK", m.BitType, "input")
     check_port(RXMOD, "data", m.ArrayType, "output")
     check_port(RXMOD, "valid", m.BitType, "output")
 
     m.compile("build/test_rxmod", RXMOD)
     assert m.testing.check_files_equal(__file__, "build/test_rxmod.v",
-            "gold/test_rxmod.v")
+            "gold/test_rxmod.v")    
 
-def test_module_arg():
+def test_basic():
     file_path = os.path.dirname(__file__)
-    RXMOD = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"), "RXMOD")
+    RXMOD = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"))[0]
 
-    check_port(RXMOD, "RX", m.BitType, "input")
-    check_port(RXMOD, "CLK", m.BitType, "input")
-    check_port(RXMOD, "data", m.ArrayType, "output")
-    check_port(RXMOD, "valid", m.BitType, "output")
+    check_rxmod(RXMOD)
+
+
+def test_target_modules_arg():
+    file_path = os.path.dirname(__file__)
+    circuits = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"), ["RXMOD"])
+    assert len(circuits) == 1
+    assert circuits[0].name == "RXMOD"
 
-    m.compile("build/test_rxmod_module_arg", RXMOD)
-    assert m.testing.check_files_equal(__file__, "build/test_rxmod_module_arg.v",
-            "gold/test_rxmod.v")
+    check_rxmod(circuits[0])