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Fix deprecation
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leonardt committed Dec 11, 2019
1 parent c981d2a commit 8a19e37
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Showing 2 changed files with 2 additions and 1 deletion.
2 changes: 1 addition & 1 deletion magma/backend/coreir_transformer.py
Original file line number Diff line number Diff line change
Expand Up @@ -196,7 +196,7 @@ def connect(self, module_defn, port, value, non_input_ports):
if value is None and is_clock_or_nested_clock(type(port)):
return
if value is None:
if port.isinout():
if port.is_inout():
return # skip inouts because they might be conn. as an input.
raise Exception(f"Found unconnected port: {port.debug_name}")

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1 change: 1 addition & 0 deletions tests/test_syntax/test_to_verilog.py
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,7 @@ def test_simple_alu():
# Test with fault if available
import fault
tester = fault.Tester(SimpleALU)
tester.circuit.CLK = 0
ops = [operator.add, operator.sub, operator.mul, operator.floordiv]
for i, op in enumerate(ops):
tester.circuit.config_ = i
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