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Add assertion to verilog deps test
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rsetaluri committed Mar 28, 2019
1 parent 96f8e69 commit 8f906a1
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Showing 2 changed files with 46 additions and 1 deletion.
42 changes: 42 additions & 0 deletions tests/test_verilog/gold/test_verilog_dependency_top.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
{"top":"global.top",
"namespaces":{
"global":{
"modules":{
"bar":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"instances":{
"foo_inst0":{
"modref":"global.foo"
}
},
"metadata":{"verilog":{"verilog_string":"module bar(input I, output O);\n foo foo_inst(I, O);\nendmodule"}}
},
"foo":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"metadata":{"verilog":{"verilog_string":"module foo(input I, output O);\n assign O = I;\nendmodule"}}
},
"top":{
"type":["Record",[
["I","BitIn"],
["O","Bit"]
]],
"instances":{
"bar_inst0":{
"modref":"global.bar"
}
},
"connections":[
["self.I","bar_inst0.I"],
["self.O","bar_inst0.O"]
]
}
}
}
}
}
5 changes: 4 additions & 1 deletion tests/test_verilog/test_from_file.py
Original file line number Diff line number Diff line change
Expand Up @@ -108,4 +108,7 @@ def test_verilog_dependency():
m.wire(top.I, bar_inst.I)
m.wire(bar_inst.O, top.O)
m.EndDefine()
m.compile("top", top, output="coreir")
FILENAME = "test_verilog_dependency_top"
m.compile(f"build/{FILENAME}", top, output="coreir")
assert m.testing.check_files_equal(__file__, f"build/{FILENAME}.json",
f"gold/{FILENAME}.json")

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