Factor into function

phanrahan · Dec 11, 2019 · 9ef1239 · 9ef1239
1 parent 6944b25
commit 9ef1239
Showing 1 changed file with 42 additions and 38 deletions.
diff --git a/magma/fromverilog.py b/magma/fromverilog.py
@@ -88,47 +88,51 @@ def convert(input_type, target_type):
     raise NotImplementedError(f"Conversion between {input_type} and "
                               f"{target_type} not supported")
 
-def get_value(v, param_map):
-    if isinstance(v, pyverilog_ast.IntConst):
-        if "'" in v.value:
-            # Parse literal specifier
-            size, value = v.value.split("'")
-            if size == "":
-                size = 32
-            else:
-                size = int(size)
-            if "s" in value:
-                signed = True
-                value = value.replace("s", "")
-            else:
-                signed = False
-            if "h" in value:
-                value = value.replace("h", "")
-                base = 16
-            elif "o" in value:
-                value = value.replace("o", "")
-                base = 8
-            elif "b" in value:
-                value = value.replace("b", "")
-                base = 2
-            elif "d" in value:
-                value = value.replace("d", "")
-                base = 10
-            else:
-                # default base 10
-                base = 10
-        else:
-            # Default no specifier
-            value = v.value
+
+def parse_int_const(value):
+    if "'" in value:
+        # Parse literal specifier
+        size, value = value.split("'")
+        if size == "":
             size = 32
-            base = 10
+        else:
+            size = int(size)
+        if "s" in value:
+            signed = True
+            value = value.replace("s", "")
+        else:
             signed = False
-        value = int(value, base)
-        if signed:
-            value = SIntVector[size](value).as_uint()
+        if "h" in value:
+            value = value.replace("h", "")
+            base = 16
+        elif "o" in value:
+            value = value.replace("o", "")
+            base = 8
+        elif "b" in value:
+            value = value.replace("b", "")
+            base = 2
+        elif "d" in value:
+            value = value.replace("d", "")
+            base = 10
         else:
-            value = UIntVector[size](value).as_uint()
-        return value
+            # default base 10
+            base = 10
+    else:
+        # Default no specifier
+        size = 32
+        base = 10
+        signed = False
+    value = int(value, base)
+    if signed:
+        value = SIntVector[size](value).as_uint()
+    else:
+        value = UIntVector[size](value).as_uint()
+    return value
+
+
+def get_value(v, param_map):
+    if isinstance(v, pyverilog_ast.IntConst):
+        return parse_int_const(v.value)
     if isinstance(v, pyverilog_ast.Rvalue):
         return get_value(v.var, param_map)
     if isinstance(v, (pyverilog_ast.Minus, pyverilog_ast.Uminus)):