Update gold

phanrahan · Dec 3, 2019 · a4041d8 · a4041d8
1 parent 153c9ae
commit a4041d8
Showing 1 changed file with 8 additions and 14 deletions.
diff --git a/tests/test_syntax/gold/TestBasicToVerilog.v b/tests/test_syntax/gold/TestBasicToVerilog.v
@@ -6,27 +6,21 @@ module TestBasic (
 );
 
 logic [1:0] _O;
-logic [1:0] self_x_I;
-logic [1:0] self_x_O;
-logic [1:0] self_y_I;
-logic [1:0] self_y_O;
+logic [1:0] x;
+logic [1:0] y;
 
 always_ff @(posedge CLK, posedge ASYNCRESET) begin
   if (ASYNCRESET) begin
-    self_x_O <= 2'h0;
-    self_y_O <= 2'h0;
+    x <= 2'h0;
+    y <= 2'h0;
   end
   else begin
-    self_x_O <= self_x_I;
-    self_y_O <= self_y_I;
+    _O <= y;
+    y <= x;
+    x <= I;
+    O <= _O;
   end
 end
-always_comb begin
-  _O = self_y_O;
-  self_y_I = self_x_O;
-  self_x_I = I;
-  O = _O;
-end
 endmodule   // TestBasic