Add sram example

examples/build/mem.json

@@ -0,0 +1,82 @@
+{"top":"global.Mem",
+"namespaces":{
+  "global":{
+    "modules":{
+      "Mem":{
+        "type":["Record",[
+          ["data_out",["Array",16,"Bit"]],
+          ["data_in",["Array",16,"BitIn"]],
+          ["clk",["Named","coreir.clkIn"]],
+          ["cen","BitIn"],
+          ["wen","BitIn"],
+          ["addr",["Array",9,"BitIn"]]
+        ]],
+        "instances":{
+          "bit_const_0_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",false]}
+          },
+          "bit_const_1_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",true]}
+          },
+          "const_0_2":{
+            "genref":"coreir.const",
+            "genargs":{"width":["Int",2]},
+            "modargs":{"value":[["BitVector",2],"2'h0"]}
+          },
+          "const_0_3":{
+            "genref":"coreir.const",
+            "genargs":{"width":["Int",3]},
+            "modargs":{"value":[["BitVector",3],"3'h0"]}
+          },
+          "mem_inst":{
+            "modref":"global.sram_512w_16b"
+          },
+          "not_inst0":{
+            "modref":"corebit.not"
+          },
+          "not_inst1":{
+            "modref":"corebit.not"
+          }
+        },
+        "connections":[
+          ["mem_inst.EMAS","bit_const_0_None.out"],
+          ["mem_inst.STOV","bit_const_0_None.out"],
+          ["mem_inst.BEN","bit_const_1_None.out"],
+          ["mem_inst.RET1N","bit_const_1_None.out"],
+          ["mem_inst.TEN","bit_const_1_None.out"],
+          ["mem_inst.EMAW","const_0_2.out"],
+          ["mem_inst.EMA","const_0_3.out"],
+          ["self.addr","mem_inst.A"],
+          ["not_inst0.out","mem_inst.CEN"],
+          ["self.clk","mem_inst.CLK"],
+          ["self.data_in","mem_inst.D"],
+          ["self.data_out","mem_inst.Q"],
+          ["not_inst1.out","mem_inst.WEN"],
+          ["self.cen","not_inst0.in"],
+          ["self.wen","not_inst1.in"]
+        ]
+      },
+      "sram_512w_16b":{
+        "type":["Record",[
+          ["Q",["Array",16,"Bit"]],
+          ["CLK",["Named","coreir.clkIn"]],
+          ["CEN","BitIn"],
+          ["WEN","BitIn"],
+          ["A",["Array",9,"BitIn"]],
+          ["D",["Array",16,"BitIn"]],
+          ["EMA",["Array",3,"BitIn"]],
+          ["EMAW",["Array",2,"BitIn"]],
+          ["EMAS","BitIn"],
+          ["TEN","BitIn"],
+          ["BEN","BitIn"],
+          ["RET1N","BitIn"],
+          ["STOV","BitIn"]
+        ]],
+        "metadata":{"verilog":{"verilog_string":"module sram_512w_16b (Q, CLK, CEN, WEN, A, D, EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV);\n   output reg [15:0] Q;\n   input        CLK;\n   input        CEN;\n   input        WEN;\n   input [8:0]  A;\n   input [15:0] D;\n   \n   input [2:0]  EMA;\n   input [1:0]  EMAW;\n   input        EMAS;\n   input        TEN;\n   input        BEN;\n   input        RET1N;\n   input        STOV;\n   \n   reg [15:0]   data_array [0:511];\n\n   always @(posedge CLK) begin\n\n      // Use all the unused wires (note at least one of them must be nonzero!)\n      if (| {EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin\n         if (CEN == 1'b0) begin                  // ACTIVE LOW!!\n            Q = data_array[A];\n            if (WEN == 1'b0) data_array[A] = D;  // ACTIVE LOW!!\n         end\n      end\n   end\nendmodule"}}
+      }
+    }
+  }
+}
+}

examples/build/mem.v

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+module sram_512w_16b (Q, CLK, CEN, WEN, A, D, EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV);
+   output reg [15:0] Q;
+   input        CLK;
+   input        CEN;
+   input        WEN;
+   input [8:0]  A;
+   input [15:0] D;
+
+   input [2:0]  EMA;
+   input [1:0]  EMAW;
+   input        EMAS;
+   input        TEN;
+   input        BEN;
+   input        RET1N;
+   input        STOV;
+
+   reg [15:0]   data_array [0:511];
+
+   always @(posedge CLK) begin
+
+      // Use all the unused wires (note at least one of them must be nonzero!)
+      if (| {EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin
+         if (CEN == 1'b0) begin                  // ACTIVE LOW!!
+            Q = data_array[A];
+            if (WEN == 1'b0) data_array[A] = D;  // ACTIVE LOW!!
+         end
+      end
+   end
+endmodule
+module coreir_const #(parameter width = 1, parameter value = 1) (output [width-1:0] out);
+  assign out = value;
+endmodule
+
+module corebit_not (input in, output out);
+  assign out = ~in;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Mem (input [8:0] addr, input cen, input clk, input [15:0] data_in, output [15:0] data_out, input wen);
+wire bit_const_0_None_out;
+wire bit_const_1_None_out;
+wire [1:0] const_0_2_out;
+wire [2:0] const_0_3_out;
+wire [15:0] mem_inst_Q;
+wire not_inst0_out;
+wire not_inst1_out;
+corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out));
+corebit_const #(.value(1)) bit_const_1_None(.out(bit_const_1_None_out));
+coreir_const #(.value(2'h0), .width(2)) const_0_2(.out(const_0_2_out));
+coreir_const #(.value(3'h0), .width(3)) const_0_3(.out(const_0_3_out));
+sram_512w_16b mem_inst(.A(addr), .BEN(bit_const_1_None_out), .CEN(not_inst0_out), .CLK(clk), .D(data_in), .EMA(const_0_3_out), .EMAS(bit_const_0_None_out), .EMAW(const_0_2_out), .Q(mem_inst_Q), .RET1N(bit_const_1_None_out), .STOV(bit_const_0_None_out), .TEN(bit_const_1_None_out), .WEN(not_inst1_out));
+corebit_not not_inst0(.in(cen), .out(not_inst0_out));
+corebit_not not_inst1(.in(wen), .out(not_inst1_out));
+assign data_out = mem_inst_Q;
+endmodule
+

examples/sram_stub.py

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+import magma as m
+# Import mantle to define operators
+import mantle
+
+
+# Returns a list of modules, select the only one
+SRAM_512W_16B = m.DefineFromVerilogFile("examples/sram_stub.v",
+                                        target_modules=["sram_512w_16b"],
+                                        # Convert CLK port from raw Bit to
+                                        # magma clock type
+                                        type_map={"CLK": m.In(m.Clock)})[0]
+
+
+# ported from
+# https://github.com/StanfordAHA/CGRAGenerator/blob/master/hardware/generator_z/memory_core/mem.vp
+class Mem(m.Circuit):
+    IO = ["data_out", m.Out(m.Bits[16]),
+          "data_in", m.In(m.Bits[16]),
+          "clk", m.In(m.Clock),
+          "cen", m.In(m.Enable),
+          "wen", m.In(m.Enable),
+          "addr", m.In(m.Bits[9])]
+
+    @classmethod
+    def definition(io):
+        # Instance sram
+        sram = SRAM_512W_16B(name="mem_inst")
+        # Wire up io
+        io.data_out <= sram.Q
+        sram.CLK <= io.clk
+        sram.A <= io.addr
+        sram.D <= io.data_in
+        # Invert control signals
+        # We convert from enable type to bit type to define invert operator
+        # (enables do not have operators by default)
+        sram.CEN <= ~m.bit(io.cen)
+        sram.WEN <= ~m.bit(io.wen)
+        # Set constants
+        sram.EMA <= 0
+        sram.EMAW <= 0
+        sram.EMAS <= 0
+        sram.TEN <= 1
+        sram.BEN <= 1
+        sram.RET1N <= 1
+        sram.STOV <= 0
+
+
+m.compile("examples/build/mem", Mem, output="coreir-verilog")

examples/sram_stub.v

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+// From https://github.com/StanfordAHA/CGRAGenerator/blob/master/verilator/generator_z_tb/sram_stub.v
+module sram_512w_16b (Q, CLK, CEN, WEN, A, D, EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV);
+   output reg [15:0] Q;
+   input        CLK;
+   input        CEN;
+   input        WEN;
+   input [8:0]  A;
+   input [15:0] D;
+
+   input [2:0]  EMA;
+   input [1:0]  EMAW;
+   input        EMAS;
+   input        TEN;
+   input        BEN;
+   input        RET1N;
+   input        STOV;
+
+   reg [15:0]   data_array [0:511];
+
+   always @(posedge CLK) begin
+
+      // Use all the unused wires (note at least one of them must be nonzero!)
+      if (| {EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin
+         if (CEN == 1'b0) begin                  // ACTIVE LOW!!
+            Q = data_array[A];
+            if (WEN == 1'b0) data_array[A] = D;  // ACTIVE LOW!!
+         end
+      end
+   end
+endmodule