Change port renaming logic for coreir frontend to use renamed_ports…

… interface
phanrahan · May 9, 2019 · ad28e3d · ad28e3d
1 parent 3d09fc2
commit ad28e3d
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Showing 3 changed files with 6 additions and 7 deletions.
diff --git a/magma/backend/coreir_.py b/magma/backend/coreir_.py
@@ -150,25 +150,25 @@ def to_string(k):
         "coreir.clkIn": Clock
     }
 
-    def get_ports(self, coreir_type):
+    def get_ports(self, coreir_type, renamed_ports):
         if (coreir_type.kind == "Bit"):
             return BitOut
         elif (coreir_type.kind == "BitIn"):
             return BitIn
         elif (coreir_type.kind == "Array"):
-            return Array[len(coreir_type), self.get_ports(coreir_type.element_type)]
+            return Array[len(coreir_type), self.get_ports(coreir_type.element_type, renamed_ports)]
         elif (coreir_type.kind == "Record"):
             elements = {}
             for item in coreir_type.items():
                 # replace  the in port with I as can't reference that
                 name = "I" if (item[0] == "in") else item[0]
-                elements[name] = self.get_ports(item[1])
+                elements[name] = self.get_ports(item[1], renamed_ports)
                 # save the renaming data for later use
                 if item[0] == "in":
                     if isinstance(elements[name], BitKind):
                         # making a copy of bit, as don't want to affect all other bits
                         elements[name] = MakeBit(direction=elements[name].direction)
-                    elements[name].origPortName = "in"
+                    renamed_ports[name] = "in"
             return Tuple(**elements)
         elif (coreir_type.kind == "Named"):
             # exception to handle clock types, since other named types not handled

diff --git a/magma/frontend/coreir_.py b/magma/frontend/coreir_.py
@@ -6,7 +6,8 @@
 def DefineModuleWrapper(cirb: CoreIRBackend, coreirModule, uniqueName, deps):
     class ModuleWrapper(Circuit):
         name = uniqueName
-        IO = cirb.get_ports_as_list(cirb.get_ports(coreirModule.type))
+        renamed_ports = {}
+        IO = cirb.get_ports_as_list(cirb.get_ports(coreirModule.type, renamed_ports))
         wrappedModule = coreirModule
         coreir_wrapped_modules_libs_used = set(deps)
 

diff --git a/magma/interface.py b/magma/interface.py
@@ -206,8 +206,6 @@ def __init__(self, renamed_ports={}, inst=None, defn=None):
             elif defn: ref = DefnRef(defn, name)
             else:      ref = AnonRef(name)
 
-            if hasattr(port, "origPortName"):
-                ref.name = port.origPortName
             if name in renamed_ports:
                 ref.name = renamed_ports[name]