Merge 8bdade4 into edd46d0

magma/backend/verilog.py

@@ -112,7 +112,7 @@ def arg(k,v):
             # find the output connected to v
             w = v.value()
             if not w:
-                logging.warning(f'{str(self.defn.name)}.{str(type(self).name)}_{self.name}.{str(v)} not connected')
+                logging.warning(f'{v.debug_name} not connected')
                 continue
             v = w
         if isinstance(k, IntegerTypes):

magma/circuit.py

@@ -6,7 +6,7 @@
     from functools import reduce
 from . import cache_definition
 import operator
-from collections import namedtuple
+from collections import namedtuple, Counter
 from .interface import *
 from .wire import *
 from .t import Flip
@@ -240,7 +240,7 @@ def debug_name(self):
         defn_str = ""
         if hasattr(self, 'defn') and self.defn is not None:
             defn_str = str(self.defn.name)
-        return f"{defn_str}_{self.name}"
+        return f"{defn_str}.{self.name}"
 
     def __call__(input, *outputs, **kw):
         debug_info = get_callee_frame_info()
@@ -264,7 +264,7 @@ def __call__(input, *outputs, **kw):
                 i = getattr(input, key)
                 wire( value, getattr(input, key), debug_info)
             else:
-                report_wiring_warning('Circuit {} does not have input {}'.format(input.debug_name, key), debug_info)
+                report_wiring_warning('Instance {} does not have input {}'.format(input.debug_name, key), debug_info)
 
         o = input.interface.outputs()
         return o[0] if len(o) == 1 else tuple(o)
@@ -436,6 +436,7 @@ def __new__(metacls, name, bases, dct):
         self.firrtl = None
 
         self._instances = []
+        self.instanced_circuits_counter = Counter()
         self._is_definition = dct.get('is_definition', False)
         self.is_instance = False
 
@@ -466,11 +467,8 @@ def instances(self):
     #
     def place(cls, inst):
         if not inst.name:
-            inst.name = 'inst' + str(len(cls.instances))
-            # osnr's suggested name
-            #inst.name = 'inst' + str(len(cls.instances)) + '_' + inst.__class__.name
-            #print('naming circuit instance', inst.name)
-        #print('placing', inst, 'in', cls)
+            inst.name = f"{type(inst).name}_inst{str(cls.instanced_circuits_counter[type(inst).name])}"
+            cls.instanced_circuits_counter[type(inst).name] += 1
         inst.defn = cls
         inst.stack = inspect.stack()
         cls.instances.append(inst)

magma/t.py

@@ -63,7 +63,7 @@ def debug_name(self):
         if isinstance(self.name, DefnRef):
             defn_str = str(self.name.defn.name) + "."
         elif isinstance(self.name, InstRef):
-            inst_str = str(type(self.name.inst).name) + "_" + str(self.name.inst.name) + "."
+            inst_str = str(self.name.inst.name) + "."
             defn_str = str(self.name.inst.defn.name) + "."
         return f"{defn_str}{inst_str}{str(self)}"
 

tests/gold/basic_function_call.json

@@ -17,15 +17,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["self.O","Mux2_inst0.O"],
+          ["self.S","Mux2_inst0.S"]
         ]
       },
       "basic_function_call":{
@@ -35,14 +35,14 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "basic_func_inst0":{
             "modref":"global.basic_func"
           }
         },
         "connections":[
-          ["self.I","inst0.I"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I","basic_func_inst0.I"],
+          ["self.O","basic_func_inst0.O"],
+          ["self.S","basic_func_inst0.S"]
         ]
       }
     }

tests/gold/basic_function_call.v

@@ -1,12 +1,12 @@
 module basic_func (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  Mux2_inst0_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(Mux2_inst0_O));
+assign O = Mux2_inst0_O;
 endmodule
 
 module basic_function_call (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-basic_func inst0 (.I(I), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  basic_func_inst0_O;
+basic_func basic_func_inst0 (.I(I), .S(S), .O(basic_func_inst0_O));
+assign O = basic_func_inst0_O;
 endmodule
 

tests/gold/if_statement_basic.json

@@ -17,15 +17,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["self.O","Mux2_inst0.O"],
+          ["self.S","Mux2_inst0.S"]
         ]
       }
     }

tests/gold/if_statement_basic.v

@@ -1,6 +1,6 @@
 module basic_if (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  Mux2_inst0_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(Mux2_inst0_O));
+assign O = Mux2_inst0_O;
 endmodule
 

tests/gold/if_statement_nested.json

@@ -17,27 +17,27 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           },
-          "inst1":{
+          "Mux2_inst1":{
             "modref":"global.Mux2"
           },
-          "inst2":{
+          "Mux2_inst2":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.3","inst0.I0"],
-          ["self.I.2","inst0.I1"],
-          ["inst2.I0","inst0.O"],
-          ["self.S.1","inst0.S"],
-          ["self.I.1","inst1.I0"],
-          ["self.I.0","inst1.I1"],
-          ["inst2.I1","inst1.O"],
-          ["self.S.1","inst1.S"],
-          ["self.O","inst2.O"],
-          ["self.S.0","inst2.S"]
+          ["self.I.3","Mux2_inst0.I0"],
+          ["self.I.2","Mux2_inst0.I1"],
+          ["Mux2_inst2.I0","Mux2_inst0.O"],
+          ["self.S.1","Mux2_inst0.S"],
+          ["self.I.1","Mux2_inst1.I0"],
+          ["self.I.0","Mux2_inst1.I1"],
+          ["Mux2_inst2.I1","Mux2_inst1.O"],
+          ["self.S.1","Mux2_inst1.S"],
+          ["self.O","Mux2_inst2.O"],
+          ["self.S.0","Mux2_inst2.S"]
         ]
       }
     }

tests/gold/if_statement_nested.v

@@ -1,10 +1,10 @@
 module if_statement_nested (input [3:0] I, input [1:0] S, output  O);
-wire  inst0_O;
-wire  inst1_O;
-wire  inst2_O;
-Mux2 inst0 (.I0(I[3]), .I1(I[2]), .S(S[1]), .O(inst0_O));
-Mux2 inst1 (.I0(I[1]), .I1(I[0]), .S(S[1]), .O(inst1_O));
-Mux2 inst2 (.I0(inst0_O), .I1(inst1_O), .S(S[0]), .O(inst2_O));
-assign O = inst2_O;
+wire  Mux2_inst0_O;
+wire  Mux2_inst1_O;
+wire  Mux2_inst2_O;
+Mux2 Mux2_inst0 (.I0(I[3]), .I1(I[2]), .S(S[1]), .O(Mux2_inst0_O));
+Mux2 Mux2_inst1 (.I0(I[1]), .I1(I[0]), .S(S[1]), .O(Mux2_inst1_O));
+Mux2 Mux2_inst2 (.I0(Mux2_inst0_O), .I1(Mux2_inst1_O), .S(S[0]), .O(Mux2_inst2_O));
+assign O = Mux2_inst2_O;
 endmodule
 

tests/gold/return_tuple.json

@@ -15,4 +15,4 @@
     }
   }
 }
-}
+}

tests/gold/simple_circuit_1.json

@@ -8,13 +8,13 @@
           ["c","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "logic_inst0":{
             "modref":"global.logic"
           }
         },
         "connections":[
-          ["self.c","inst0.O0"],
-          ["self.a","inst0.a"]
+          ["self.c","logic_inst0.O0"],
+          ["self.a","logic_inst0.a"]
         ]
       },
       "Mux2":{
@@ -47,6 +47,9 @@
           ["O0","Bit"]
         ]],
         "instances":{
+          "Mux2_inst0":{
+            "modref":"global.Mux2"
+          },
           "bit_const_0_None":{
             "modref":"corebit.const",
             "modargs":{"value":["Bool",false]}
@@ -55,20 +58,17 @@
             "modref":"corebit.const",
             "modargs":{"value":["Bool",true]}
           },
-          "inst0":{
+          "eq_inst0":{
             "modref":"global.eq"
-          },
-          "inst1":{
-            "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["inst0.I1","bit_const_0_None.out"],
-          ["inst1.I0","bit_const_0_None.out"],
-          ["inst1.I1","bit_const_1_None.out"],
-          ["self.a","inst0.I0"],
-          ["inst1.S","inst0.O"],
-          ["self.O0","inst1.O"]
+          ["bit_const_0_None.out","Mux2_inst0.I0"],
+          ["bit_const_1_None.out","Mux2_inst0.I1"],
+          ["self.O0","Mux2_inst0.O"],
+          ["eq_inst0.O","Mux2_inst0.S"],
+          ["eq_inst0.I1","bit_const_0_None.out"],
+          ["self.a","eq_inst0.I0"]
         ]
       }
     }

tests/gold/ternary.json

@@ -17,15 +17,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["self.O","Mux2_inst0.O"],
+          ["self.S","Mux2_inst0.S"]
         ]
       }
     }

tests/gold/ternary.v

@@ -1,6 +1,6 @@
 module ternary (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  Mux2_inst0_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(Mux2_inst0_O));
+assign O = Mux2_inst0_O;
 endmodule
 

tests/gold/ternary_nested.json

@@ -17,21 +17,21 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           },
-          "inst1":{
+          "Mux2_inst1":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.2","inst0.I0"],
-          ["self.I.1","inst0.I1"],
-          ["inst1.I0","inst0.O"],
-          ["self.S.1","inst0.S"],
-          ["self.I.0","inst1.I1"],
-          ["self.O","inst1.O"],
-          ["self.S.0","inst1.S"]
+          ["self.I.2","Mux2_inst0.I0"],
+          ["self.I.1","Mux2_inst0.I1"],
+          ["Mux2_inst1.I0","Mux2_inst0.O"],
+          ["self.S.1","Mux2_inst0.S"],
+          ["self.I.0","Mux2_inst1.I1"],
+          ["self.O","Mux2_inst1.O"],
+          ["self.S.0","Mux2_inst1.S"]
         ]
       }
     }

tests/gold/ternary_nested.v

@@ -1,8 +1,8 @@
 module ternary_nested (input [3:0] I, input [1:0] S, output  O);
-wire  inst0_O;
-wire  inst1_O;
-Mux2 inst0 (.I0(I[2]), .I1(I[1]), .S(S[1]), .O(inst0_O));
-Mux2 inst1 (.I0(inst0_O), .I1(I[0]), .S(S[0]), .O(inst1_O));
-assign O = inst1_O;
+wire  Mux2_inst0_O;
+wire  Mux2_inst1_O;
+Mux2 Mux2_inst0 (.I0(I[2]), .I1(I[1]), .S(S[1]), .O(Mux2_inst0_O));
+Mux2 Mux2_inst1 (.I0(Mux2_inst0_O), .I1(I[0]), .S(S[0]), .O(Mux2_inst1_O));
+assign O = Mux2_inst1_O;
 endmodule
 

tests/gold/ternary_nested2.json

@@ -17,21 +17,21 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           },
-          "inst1":{
+          "Mux2_inst1":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["inst1.I1","inst0.O"],
-          ["self.S.0","inst0.S"],
-          ["self.I.2","inst1.I0"],
-          ["self.O","inst1.O"],
-          ["self.S.1","inst1.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["Mux2_inst1.I1","Mux2_inst0.O"],
+          ["self.S.0","Mux2_inst0.S"],
+          ["self.I.2","Mux2_inst1.I0"],
+          ["self.O","Mux2_inst1.O"],
+          ["self.S.1","Mux2_inst1.S"]
         ]
       }
     }

tests/gold/ternary_nested2.v

@@ -1,8 +1,8 @@
 module ternary_nested2 (input [3:0] I, input [1:0] S, output  O);
-wire  inst0_O;
-wire  inst1_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S[0]), .O(inst0_O));
-Mux2 inst1 (.I0(I[2]), .I1(inst0_O), .S(S[1]), .O(inst1_O));
-assign O = inst1_O;
+wire  Mux2_inst0_O;
+wire  Mux2_inst1_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S[0]), .O(Mux2_inst0_O));
+Mux2 Mux2_inst1 (.I0(I[2]), .I1(Mux2_inst0_O), .S(S[1]), .O(Mux2_inst1_O));
+assign O = Mux2_inst1_O;
 endmodule