Merge c622562 into 2e51b72

phanrahan · Mar 21, 2019 · ddda928 · ddda928
2 parents 2e51b72 + c622562
commit ddda928
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Showing 4 changed files with 9 additions and 7 deletions.
diff --git a/magma/array.py b/magma/array.py
@@ -73,7 +73,9 @@ def flip(cls):
 
     def __call__(cls, *args, **kwargs):
         result = super().__call__(*args, **kwargs)
-        if len(args) == 1 and isinstance(args[0], Array):
+        if len(args) == 1 and isinstance(args[0], Array) and not \
+                issubclass(cls.T, Array) and args[0] == cls.N \
+                and args[0].T == cls.T:
             arg = args[0]
             if len(arg) < len(result):
                 from .conversions import zext

diff --git a/magma/bits.py b/magma/bits.py
@@ -17,10 +17,10 @@ class BitsKind(ArrayKind):
 
     def __str__(cls):
         if cls.isinput():
-            return "In(Bits({}))".format(cls.N)
+            return "In(Bits[{}])".format(cls.N)
         if cls.isoutput():
-            return "Out(Bits({}))".format(cls.N)
-        return "Bits({})".format(cls.N)
+            return "Out(Bits[{}])".format(cls.N)
+        return "Bits[{}]".format(cls.N)
 
 
     def __getitem__(cls, index):

diff --git a/tests/test_interface/test_interface.py b/tests/test_interface/test_interface.py
@@ -6,10 +6,10 @@
 
 def test_1():
     I0 = DeclareInterface("a", In(Bit), "b", Out(Bits[2]))
-    assert str(I0) == '"a", In(Bit), "b", Out(Bits(2))'
+    assert str(I0) == '"a", In(Bit), "b", Out(Bits[2])'
 
     i0 = I0()
     print(i0)
-    assert str(i0) == '"a", In(Bit), "b", Out(Bits(2))'
+    assert str(i0) == '"a", In(Bit), "b", Out(Bits[2])'
 
 
diff --git a/tests/test_verilog/test_from_file.py b/tests/test_verilog/test_from_file.py
@@ -71,7 +71,7 @@ def test_decl_list():
     memory_core = m.DefineFromVerilogFile(
         os.path.join(file_path, "decl_list.v"), target_modules=["memory_core"],
         type_map=type_map)[0]
-    assert str(memory_core) == "memory_core(clk_in: In(Clock), clk_en: In(Enable), reset: In(AsyncReset), config_addr: In(Bits(32)), config_data: In(Bits(32)), config_read: In(Bit), config_write: In(Bit), config_en: In(Enable), config_en_sram: In(Bits(4)), config_en_linebuf: In(Bit), data_in: In(Bits(16)), data_out: Out(Bits(16)), wen_in: In(Bit), ren_in: In(Bit), valid_out: Out(Bit), chain_in: In(Bits(16)), chain_out: Out(Bits(16)), chain_wen_in: In(Bit), chain_valid_out: Out(Bit), almost_full: Out(Bit), almost_empty: Out(Bit), addr_in: In(Bits(16)), read_data: Out(Bits(32)), read_data_sram: Out(Bits(32)), read_data_linebuf: Out(Bits(32)), flush: In(Bit))"
+    assert str(memory_core) == "memory_core(clk_in: In(Clock), clk_en: In(Enable), reset: In(AsyncReset), config_addr: In(Bits[32]), config_data: In(Bits[32]), config_read: In(Bit), config_write: In(Bit), config_en: In(Enable), config_en_sram: In(Bits[4]), config_en_linebuf: In(Bit), data_in: In(Bits[16]), data_out: Out(Bits[16]), wen_in: In(Bit), ren_in: In(Bit), valid_out: Out(Bit), chain_in: In(Bits[16]), chain_out: Out(Bits[16]), chain_wen_in: In(Bit), chain_valid_out: Out(Bit), almost_full: Out(Bit), almost_empty: Out(Bit), addr_in: In(Bits[16]), read_data: Out(Bits[32]), read_data_sram: Out(Bits[32]), read_data_linebuf: Out(Bits[32]), flush: In(Bit))"
 
 
 def test_from_sv():