Merge 8597657 into 26878fd

phanrahan · Oct 19, 2018 · eed3dcf · eed3dcf
2 parents 26878fd + 8597657
commit eed3dcf
Showing 1 changed file with 8 additions and 14 deletions.
diff --git a/magma/fromverilog.py b/magma/fromverilog.py
@@ -107,7 +107,7 @@ def ParseVerilogModule(node, type_map):
 
     return node.name, args
 
-def FromVerilog(source, func, type_map, module=None):
+def FromVerilog(source, func, type_map, target_modules=None):
     parser = VerilogParser()
 
     ast = parser.parse(source)
@@ -121,7 +121,7 @@ def FromVerilog(source, func, type_map, module=None):
         assert len(v.nodes) == 1
     modules = []
     for node in v.nodes:
-        if module is not None and node.name != module:
+        if target_modules is not None and node.name not in target_modules:
             continue
         try:
             name, args = ParseVerilogModule(node, type_map)
@@ -130,23 +130,17 @@ def FromVerilog(source, func, type_map, module=None):
                 # inline source
                 circuit.verilogFile = source
                 EndDefine()
-            if module is not None:
-                assert node.name == module
-                return circuit
             modules.append(circuit)
         except Exception as e:
             logger.warning(f"Could not parse module {node.name} ({e}), "
                            f"skipping")
-    if module is not None:
-        raise Exception(f"Could not find module {module}")
-
     return modules
 
-def FromVerilogFile(file, func, type_map, module=None):
+def FromVerilogFile(file, func, type_map, target_modules=None):
     if file is None:
         return None
     verilog = open(file).read()
-    return FromVerilog(verilog, func, type_map, module)
+    return FromVerilog(verilog, func, type_map, target_modules)
 
 def FromTemplatedVerilog(templatedverilog, func, type_map, **kwargs):
     verilog = Template(templatedverilog).render(**kwargs)
@@ -162,8 +156,8 @@ def FromTemplatedVerilogFile(file, func, type_map, **kwargs):
 def DeclareFromVerilog(source, type_map={}):
     return FromVerilog(source, DeclareCircuit, type_map)
 
-def DeclareFromVerilogFile(file, module=None, type_map={}):
-    return FromVerilogFile(file, DeclareCircuit, type_map, module)
+def DeclareFromVerilogFile(file, target_modules=None, type_map={}):
+    return FromVerilogFile(file, DeclareCircuit, type_map, target_modules)
 
 def DeclareFromTemplatedVerilog(source, type_map={}, **kwargs):
     return FromTemplatedVerilog(source, DeclareCircuit, type_map, **kwargs)
@@ -175,8 +169,8 @@ def DeclareFromTemplatedVerilogFile(file, type_map={}, **kwargs):
 def DefineFromVerilog(source, type_map={}):
     return FromVerilog(source, DefineCircuit, type_map)
 
-def DefineFromVerilogFile(file, module=None, type_map={}):
-    return FromVerilogFile(file, DefineCircuit, type_map, module)
+def DefineFromVerilogFile(file, target_modules=None, type_map={}):
+    return FromVerilogFile(file, DefineCircuit, type_map, target_modules)
 
 def DefineFromTemplatedVerilog(source, type_map={}, **kwargs):
     return FromTemplatedVerilog(source, DefineCircuit, type_map, **kwargs)