Merge branch 'master' into coreir-conn-metadata

.travis.yml

@@ -2,7 +2,12 @@ language: python
 python:
     - "3.6"
 
-sudo: true  # Needed for coreir-dev branch building coreir from source (installing g++-4.9 through apt)
+addons:
+  apt:
+    sources:
+      - ubuntu-toolchain-r-test
+    packages:
+      - g++-4.9
 
 before_install:
     - source .travis/install_coreir.sh

.travis/install_coreir.sh

@@ -3,9 +3,6 @@
 set -e
 
 if [ "$TRAVIS_BRANCH" == "coreir-dev" ]; then
-    sudo add-apt-repository -y ppa:ubuntu-toolchain-r/test
-    sudo apt-get update
-    sudo apt-get install g++-4.9
     mkdir deps;
     mkdir deps/bin;
     mkdir deps/lib;

magma/backend/coreir_.py

@@ -16,6 +16,7 @@
 from .util import make_relative, get_codegen_debug_info
 from ..interface import InterfaceKind
 import inspect
+import copy
 
 from collections import defaultdict
 
@@ -254,7 +255,7 @@ def compile_definition_to_module_definition(self, definition, module_definition)
             self.libs_used.add(definition.coreir_lib)
         output_ports = {}
         for name, port in definition.interface.ports.items():
-            logger.debug(name, port, port.isoutput())
+            logger.debug("{}, {}, {}".format(name, port, port.isoutput()))
             self.add_output_port(output_ports, port)
 
         for instance in definition.instances:
@@ -406,9 +407,12 @@ def compile(self, defn_or_declaration):
             # don't try to compile if already have definition
             if hasattr(defn_or_declaration, 'wrappedModule'):
                 self.modules[defn_or_declaration.name] = defn_or_declaration.wrappedModule
+                self.libs_used |= defn_or_declaration.coreir_wrapped_modules_libs_used
             else:
                 self.modules[defn_or_declaration.name] = self.compile_definition(defn_or_declaration)
                 defn_or_declaration.wrappedModule = self.modules[defn_or_declaration.name]
+                defn_or_declaration.coreir_wrapped_modules_libs_used = \
+                    copy.copy(self.libs_used)
         else:
             self.modules[defn_or_declaration.name] = self.compile_declaration(defn_or_declaration)
         return self.modules

magma/bits.py

@@ -2,9 +2,10 @@
 from .ref import AnonRef
 from .bit import Bit, VCC, GND
 from .array import ArrayType, ArrayKind
-from .bit_vector import BitVector, SIntVector
 from .debug import debug_wire
 
+from bit_vector import BitVector, SIntVector
+
 __all__ = ['Bits', 'BitsType', 'BitsKind']
 __all__ += ['UInt', 'UIntType', 'UIntKind']
 __all__ += ['SInt', 'SIntType', 'SIntKind']

magma/circuit.py

@@ -180,11 +180,13 @@ def set_debug_info(self, debug_info):
         self.debug_info = debug_info
 
     def __str__(self):
-        name = self.name if self.name else f"AnonymousCircuitType{id(self)}"
-        interface = ""
-        interface = ", ".join(f"{name}: {type(value)}" for name, value in self.interface.ports.items())
-        interface = f"({interface})"
-        return f"{name}{interface}"
+        if self.name:
+            return f"{self.name}<{type(self)}>"
+        else:
+            name = f"AnonymousCircuitInst{id(self)}"
+            interface = ""
+            interface = ", ".join(f"{name}: {type(value)}" for name, value in self.interface.ports.items())
+            return f"{name}<{interface}>"
 
     def __repr__(self):
         args = []

magma/compile.py

@@ -67,7 +67,8 @@ def __init__(self, main):
         self.has_mantle_circuit = False
 
     def __call__(self, definition):
-        if definition.debug_info.module.__name__.split(".")[0] == "mantle":
+        if definition.debug_info.module is not None and \
+                definition.debug_info.module.__name__.split(".")[0] == "mantle":
             self.has_mantle_circuit = True
 
     def _run(self, definition):

magma/fromverilog.py

@@ -6,6 +6,7 @@
 from pyverilog.vparser.parser import VerilogParser, Node, Input, Output, ModuleDef, Ioport, Port, Decl
 import pyverilog.vparser.parser as parser
 from pyverilog.dataflow.visit import NodeVisitor
+import pyverilog.vparser.ast as pyverilog_ast
 
 from .t import In, Out, InOut
 from .bit import Bit, _BitKind
@@ -46,6 +47,13 @@ def convert(input_type, target_type):
     raise NotImplementedError(f"Conversion between {input_type} and "
                               f"{target_type} not supported")
 
+def get_value(v):
+    if isinstance(v, pyverilog_ast.IntConst):
+        return int(v.value)
+    if isinstance(v, pyverilog_ast.Minus):
+        return get_value(v.left) - get_value(v.right)
+    else:
+        raise NotImplementedError(type(v))
 
 def get_type(io, type_map):
     if isinstance(io, Input):
@@ -58,8 +66,8 @@ def get_type(io, type_map):
     if io.width is None:
         type_ = Bit
     else:
-        msb = int(io.width.msb.value)
-        lsb = int(io.width.lsb.value)
+        msb = get_value(io.width.msb)
+        lsb = get_value(io.width.lsb)
         type_ = Bits(msb-lsb+1)
 
     type_ = direction(type_)
@@ -99,7 +107,7 @@ def ParseVerilogModule(node, type_map):
 
     return node.name, args
 
-def FromVerilog(source, func, type_map, module=None):
+def FromVerilog(source, func, type_map, target_modules=None):
     parser = VerilogParser()
 
     ast = parser.parse(source)
@@ -109,11 +117,14 @@ def FromVerilog(source, func, type_map, module=None):
     v.visit(ast)
 
     if func == DefineCircuit:
-        # only allow a single verilog module
-        assert len(v.nodes) == 1
+        # only allow a single verilog module unless we're only defining one
+        # circuit (only one module in target_modules), otherwise, they would
+        # all use the same source, so if they are compiled together, there will
+        # be multiple definitions of the same verilog module
+        assert len(v.nodes) == 1 or len(target_modules) == 1
     modules = []
     for node in v.nodes:
-        if module is not None and node.name != module:
+        if target_modules is not None and node.name not in target_modules:
             continue
         try:
             name, args = ParseVerilogModule(node, type_map)
@@ -122,23 +133,22 @@ def FromVerilog(source, func, type_map, module=None):
                 # inline source
                 circuit.verilogFile = source
                 EndDefine()
-            if module is not None:
-                assert node.name == module
-                return circuit
+            circuit.verilog_source = source
             modules.append(circuit)
         except Exception as e:
             logger.warning(f"Could not parse module {node.name} ({e}), "
                            f"skipping")
-    if module is not None:
-        raise Exception(f"Could not find module {module}")
-
+    if not modules:
+        logger.warning(f"Did not import any modules from verilog, either could "
+                       f"not parse or could not find any of the target_modules "
+                       f"({target_modules})")
     return modules
 
-def FromVerilogFile(file, func, type_map, module=None):
+def FromVerilogFile(file, func, type_map, target_modules=None):
     if file is None:
         return None
     verilog = open(file).read()
-    return FromVerilog(verilog, func, type_map, module)
+    return FromVerilog(verilog, func, type_map, target_modules)
 
 def FromTemplatedVerilog(templatedverilog, func, type_map, **kwargs):
     verilog = Template(templatedverilog).render(**kwargs)
@@ -154,8 +164,8 @@ def FromTemplatedVerilogFile(file, func, type_map, **kwargs):
 def DeclareFromVerilog(source, type_map={}):
     return FromVerilog(source, DeclareCircuit, type_map)
 
-def DeclareFromVerilogFile(file, module=None, type_map={}):
-    return FromVerilogFile(file, DeclareCircuit, type_map, module)
+def DeclareFromVerilogFile(file, target_modules=None, type_map={}):
+    return FromVerilogFile(file, DeclareCircuit, type_map, target_modules)
 
 def DeclareFromTemplatedVerilog(source, type_map={}, **kwargs):
     return FromTemplatedVerilog(source, DeclareCircuit, type_map, **kwargs)
@@ -164,11 +174,11 @@ def DeclareFromTemplatedVerilogFile(file, type_map={}, **kwargs):
     return FromTemplatedVerilogFile(file, DeclareCircuit, type_map, **kwargs)
 
 
-def DefineFromVerilog(source, type_map={}):
-    return FromVerilog(source, DefineCircuit, type_map)
+def DefineFromVerilog(source, type_map={}, target_modules=None):
+    return FromVerilog(source, DefineCircuit, type_map, target_modules)
 
-def DefineFromVerilogFile(file, module=None, type_map={}):
-    return FromVerilogFile(file, DefineCircuit, type_map, module)
+def DefineFromVerilogFile(file, target_modules=None, type_map={}):
+    return FromVerilogFile(file, DefineCircuit, type_map, target_modules)
 
 def DefineFromTemplatedVerilog(source, type_map={}, **kwargs):
     return FromTemplatedVerilog(source, DefineCircuit, type_map, **kwargs)

magma/simulator/coreir_simulator.py

@@ -135,7 +135,7 @@ def __init__(self, circuit, clock, coreir_filename=None, context=None, namespace
         self.ctx.enable_symbol_table()
         coreir_circuit = self.ctx.load_from_file(coreir_filename)
         self.ctx.run_passes(["rungenerators", "wireclocks-coreir", "verifyconnectivity --noclkrst",
-                             "flattentypes", "flatten", "verifyconnectivity --noclkrst", "deletedeadinstances"],
+                             "flattentypes", "flatten", "deletedeadinstances"],
                             namespaces=namespaces)
         self.simulator_state = coreir.SimulatorState(coreir_circuit)
 

magma/simulator/python_simulator.py

@@ -14,7 +14,7 @@
 from ..bit import VCC, GND, BitType, _BitType
 from ..array import ArrayType
 from ..bits import SIntType, BitsType, UIntType
-from ..bit_vector import BitVector
+from bit_vector import BitVector
 from ..bitutils import seq2int
 from ..clock import ClockType
 

magma/testing/coroutine.py

@@ -1,5 +1,5 @@
 from magma.simulator import PythonSimulator
-from magma.bit_vector import BitVector
+from bit_vector import BitVector
 
 class Coroutine:
     """

setup.py

@@ -22,8 +22,8 @@
         "pyverilog",
         "numpy",
         "graphviz",
-        "coreir >=0.24a0, <= 0.26a0",
-        "bit_vector==0.36a0"
+        "coreir==0.29a0",
+        "bit_vector==0.39a0"
     ],
     python_requires='>=3.6'
 )

tests/test_circuit/test_inspect.py

@@ -0,0 +1,47 @@
+import magma as m
+
+
+def test_str_repr():
+    And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit),
+                            "O", m.Out(m.Bit))
+    XOr2 = m.DeclareCircuit('XOr2', "I0", m.In(m.Bit), "I1", m.In(m.Bit),
+                            "O", m.Out(m.Bit))
+    Logic2 = m.DefineCircuit('Logic2', 'I0', m.In(m.Bit), 'I1', m.In(m.Bit), 'O', m.Out(m.Bit))
+    m.wire(XOr2()(And2()(Logic2.I0, Logic2.I1), 1), Logic2.O)
+    m.EndCircuit()
+
+    assert str(Logic2) == "Logic2(I0: In(Bit), I1: In(Bit), O: Out(Bit))"
+    assert repr(Logic2) == """\
+Logic2 = DefineCircuit("Logic2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
+inst0 = XOr2()
+inst1 = And2()
+wire(inst1.O, inst0.I0)
+wire(1, inst0.I1)
+wire(Logic2.I0, inst1.I0)
+wire(Logic2.I1, inst1.I1)
+wire(inst0.O, Logic2.O)
+EndCircuit()\
+"""
+
+    expected = [
+        "inst0<XOr2(I0: In(Bit), I1: In(Bit), O: Out(Bit))>",
+        "inst1<And2(I0: In(Bit), I1: In(Bit), O: Out(Bit))>"
+    ]
+    for inst, expected in zip(Logic2.instances, expected):
+        assert str(inst) == expected
+
+
+def test_str_repr_anon():
+    And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit),
+                            "O", m.Out(m.Bit))
+    circ = m.DefineCircuit("Test", "I0", m.In(m.Bits(3)), "I1", m.In(m.Bits(3)), "O", m.Out(m.Bits(3)))
+    anon = m.join(m.map_(And2, 3))
+    m.wire(circ.I0, anon.I0)
+    m.wire(circ.I1, anon.I1)
+    m.wire(circ.O, anon.O)
+    m.EndCircuit()
+
+    string = str(anon)
+    assert string[:len("AnonymousCircuitInst")] == "AnonymousCircuitInst"
+    assert string[-len("<I0: Array(3,In(Bit)), I1: Array(3,In(Bit)), O: Array(3,Out(Bit))>"):] == "<I0: Array(3,In(Bit)), I1: Array(3,In(Bit)), O: Array(3,Out(Bit))>"
+    assert repr(anon) == 'AnonymousCircuitType("I0", array([inst0.I0, inst1.I0, inst2.I0]), "I1", array([inst0.I1, inst1.I1, inst2.I1]), "O", array([inst0.O, inst1.O, inst2.O]))'

tests/test_coreir/gold/test_compile_coreir_verilog.v

@@ -1,11 +1,19 @@
-//Module: And2 defined externally
+/* External Modules
+module And2 (
+  input  I0,
+  input  I1,
+  output  O
+);
 
+endmodule  // And2
 
+*/
 module main (
   input [1:0] I,
   output  O
 );
-  //Wire declarations for instance 'inst0' (Module And2)
+
+
   wire  inst0__I0;
   wire  inst0__I1;
   wire  inst0__O;
@@ -15,9 +23,12 @@ module main (
     .O(inst0__O)
   );
 
-  //All the connections
   assign inst0__I0 = I[0];
+
   assign inst0__I1 = I[1];
+
   assign O = inst0__O;
 
-endmodule //main
+
+endmodule  // main
+

tests/test_type/gold/test_enum.v

@@ -1,25 +1,27 @@
-
-
 module coreir_const #(parameter value=1, parameter width=1) (
   output [width-1:0] out
 );
   assign out = value;
 
-endmodule //coreir_const
+endmodule  // coreir_const
 
 module enum_test (
   input [1:0] I,
   output [1:0] O_0,
   output [1:0] O_1
 );
-  //Wire declarations for instance 'const_0_2' (Module coreir_const)
+
+
+  // Instancing generated Module: coreir.const(width:2)
   wire [1:0] const_0_2__out;
-  coreir_const #(.value(2'b00),.width(2)) const_0_2(
+  coreir_const #(.value(2'h0),.width(2)) const_0_2(
     .out(const_0_2__out)
   );
 
-  //All the connections
   assign O_1[1:0] = const_0_2__out[1:0];
+
   assign O_0[1:0] = I[1:0];
 
-endmodule //enum_test
+
+endmodule  // enum_test
+