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Update coreir backend to support arrays of mixed direction #274

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merged 1 commit into from
Sep 6, 2018
Merged

Update coreir backend to support arrays of mixed direction #274

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20 changes: 7 additions & 13 deletions magma/backend/coreir_.py
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Original file line number Diff line number Diff line change
Expand Up @@ -104,9 +104,9 @@ def check_type(port, errorMessage=""):
for name, port in definition.interface.ports.items():
check_type(type(port), 'Error: Argument {} must be comprised only of Bit, Array, or Tuple')

def get_type(self, port, is_input):
def get_type(self, port):
if isinstance(port, (ArrayType, ArrayKind)):
_type = self.context.Array(port.N, self.get_type(port.T, is_input))
_type = self.context.Array(port.N, self.get_type(port.T))
elif isinstance(port, (TupleType, TupleKind)):
def to_string(k):
"""
Expand All @@ -119,10 +119,10 @@ def to_string(k):
return f"_{k}"
return k
_type = self.context.Record({
to_string(k): self.get_type(t, t.isinput()) for (k, t) in
to_string(k): self.get_type(t) for (k, t) in
zip(port.Ks, port.Ts)
})
elif is_input:
elif port.isinput():
if isinstance(port, (ClockType, ClockKind)):
_type = self.context.named_types[("coreir", "clk")]
elif isinstance(port, (AsyncResetType, AsyncResetKind)):
Expand Down Expand Up @@ -178,10 +178,7 @@ def get_ports_as_list(self, ports):
def convert_interface_to_module_type(self, interface):
args = OrderedDict()
for name, port in interface.ports.items():
if not port.isinput() and not port.isoutput() and \
not isinstance(port, TupleType):
raise NotImplementedError()
args[name] = self.get_type(port, port.isinput())
args[name] = self.get_type(port)
return self.context.Record(args)

def compile_instance(self, instance, module_definition):
Expand Down Expand Up @@ -221,10 +218,7 @@ def compile_instance(self, instance, module_definition):
def add_output_port(self, output_ports, port):
if port.isoutput():
output_ports[port] = magma_port_to_coreir(port)
if isinstance(port, ArrayType):
for element in port:
self.add_output_port(output_ports, element)
if isinstance(port, TupleType):
if isinstance(port, (TupleType, ArrayType)):
for element in port:
self.add_output_port(output_ports, element)

Expand Down Expand Up @@ -275,7 +269,7 @@ def compile_definition_to_module_definition(self, definition, module_definition)
def connect_input(self, module_definition, port,
output_ports):
if not port.isinput():
if isinstance(port, TupleType):
if isinstance(port, (TupleType, ArrayType)):
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good for now, but is there some more general way of doing this?

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Any ideas? The idea here is that if a type has mixed directions, we need to descend to its children to check whether there are any inputs that need to be wired. In this case, we just have a tuple of types that have mixed direction children. Maybe we could add a field marking these special types? I think this covers the desired functionality though so I'm not sure what benefit making this more general would provide, or in fact what making it more general even means? Does that mean if we add another type with mixed directionality that it will still work?

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Good point. I think the key thing is for new types with mixed direction (if such a use case even exists). The most right way to do it is require all types to implement some methods which provide some information about mixed types (or expose some tree like structure so we can generically explore the type hierarchy and reach the leaves). Again, for now it covers our cases. We could say that all such new types are not supported directly in CoreIR anyway so our backend doesn't support them unless you special case it.

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One thing is to consider whether these mixed directional types are built on top of array/tuple. If so, this should just work. If not, then I think we should consider this API for determining directionality that types will need to implement.

for elem in port:
self.connect_input(module_definition, elem,
output_ports)
Expand Down
25 changes: 25 additions & 0 deletions tests/test_coreir/gold/test_array_nesting.json
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Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
{"top":"global.Foo",
"namespaces":{
"global":{
"modules":{
"Foo":{
"type":["Record",[
["IFC",["Array",10,["Record",[["I","BitIn"],["O","Bit"]]]]]
]],
"connections":[
["self.IFC.0.O","self.IFC.0.I"],
["self.IFC.1.O","self.IFC.1.I"],
["self.IFC.2.O","self.IFC.2.I"],
["self.IFC.3.O","self.IFC.3.I"],
["self.IFC.4.O","self.IFC.4.I"],
["self.IFC.5.O","self.IFC.5.I"],
["self.IFC.6.O","self.IFC.6.I"],
["self.IFC.7.O","self.IFC.7.I"],
["self.IFC.8.O","self.IFC.8.I"],
["self.IFC.9.O","self.IFC.9.I"]
]
}
}
}
}
}
10 changes: 10 additions & 0 deletions tests/test_coreir/test_coreir_tuple.py
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Original file line number Diff line number Diff line change
Expand Up @@ -64,5 +64,15 @@ def test_nesting():
assert check_files_equal(__file__, f"build/test_nesting.json",
f"gold/test_nesting.json")

def test_array_nesting():
T = m.Array(10, m.Tuple(I=m.In(m.Bit), O=m.Out(m.Bit)))
Foo = m.DefineCircuit("Foo", "IFC", T)
for i in range(10):
m.wire(Foo.IFC[i].I, Foo.IFC[i].O)
m.EndCircuit()
m.compile("build/test_array_nesting", Foo, output="coreir")
assert check_files_equal(__file__, f"build/test_array_nesting.json",
f"gold/test_array_nesting.json")

if __name__ == "__main__":
test_multi_direction_tuple()