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Fix an issue with nested array call logic #372

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Mar 21, 2019
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3 changes: 2 additions & 1 deletion magma/array.py
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,8 @@ def flip(cls):

def __call__(cls, *args, **kwargs):
result = super().__call__(*args, **kwargs)
if len(args) == 1 and isinstance(args[0], Array):
if len(args) == 1 and isinstance(args[0], Array) and not \
(issubclass(cls.T, Array) and cls.N == 1):
arg = args[0]
if len(arg) < len(result):
from .conversions import zext
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6 changes: 3 additions & 3 deletions magma/bits.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,10 @@ class BitsKind(ArrayKind):

def __str__(cls):
if cls.isinput():
return "In(Bits({}))".format(cls.N)
return "In(Bits[{}])".format(cls.N)
if cls.isoutput():
return "Out(Bits({}))".format(cls.N)
return "Bits({})".format(cls.N)
return "Out(Bits[{}])".format(cls.N)
return "Bits[{}]".format(cls.N)


def __getitem__(cls, index):
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4 changes: 2 additions & 2 deletions tests/test_interface/test_interface.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@

def test_1():
I0 = DeclareInterface("a", In(Bit), "b", Out(Bits[2]))
assert str(I0) == '"a", In(Bit), "b", Out(Bits(2))'
assert str(I0) == '"a", In(Bit), "b", Out(Bits[2])'

i0 = I0()
print(i0)
assert str(i0) == '"a", In(Bit), "b", Out(Bits(2))'
assert str(i0) == '"a", In(Bit), "b", Out(Bits[2])'


2 changes: 1 addition & 1 deletion tests/test_verilog/test_from_file.py
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ def test_decl_list():
memory_core = m.DefineFromVerilogFile(
os.path.join(file_path, "decl_list.v"), target_modules=["memory_core"],
type_map=type_map)[0]
assert str(memory_core) == "memory_core(clk_in: In(Clock), clk_en: In(Enable), reset: In(AsyncReset), config_addr: In(Bits(32)), config_data: In(Bits(32)), config_read: In(Bit), config_write: In(Bit), config_en: In(Enable), config_en_sram: In(Bits(4)), config_en_linebuf: In(Bit), data_in: In(Bits(16)), data_out: Out(Bits(16)), wen_in: In(Bit), ren_in: In(Bit), valid_out: Out(Bit), chain_in: In(Bits(16)), chain_out: Out(Bits(16)), chain_wen_in: In(Bit), chain_valid_out: Out(Bit), almost_full: Out(Bit), almost_empty: Out(Bit), addr_in: In(Bits(16)), read_data: Out(Bits(32)), read_data_sram: Out(Bits(32)), read_data_linebuf: Out(Bits(32)), flush: In(Bit))"
assert str(memory_core) == "memory_core(clk_in: In(Clock), clk_en: In(Enable), reset: In(AsyncReset), config_addr: In(Bits[32]), config_data: In(Bits[32]), config_read: In(Bit), config_write: In(Bit), config_en: In(Enable), config_en_sram: In(Bits[4]), config_en_linebuf: In(Bit), data_in: In(Bits[16]), data_out: Out(Bits[16]), wen_in: In(Bit), ren_in: In(Bit), valid_out: Out(Bit), chain_in: In(Bits[16]), chain_out: Out(Bits[16]), chain_wen_in: In(Bit), chain_valid_out: Out(Bit), almost_full: Out(Bit), almost_empty: Out(Bit), addr_in: In(Bits[16]), read_data: Out(Bits[32]), read_data_sram: Out(Bits[32]), read_data_linebuf: Out(Bits[32]), flush: In(Bit))"


def test_from_sv():
Expand Down