Share setports logic for defn/decl

[leonardt]

Right now circuits declared using m.DeclareCircuit do not have attributes corresponding to their ports, so the following simple test fails:

import magma as m
And2 = m.DeclareCircuit("And2", "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O", m.Out(m.Bit))
assert isinstance(And2.I0, m.BitType)

with

Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
AttributeError: type object 'And2' has no attribute 'I0'

The logic to set the port attributes is contained with DefineCircuitKind.__new__, so it's only used for definitions, whereas in CircuitKind.__new__ the interface is never instantiated nor is setports called.

These changes move the cls.interface = cls.IO(...) instantiation and setports logic to CircuitKind.__new__ so both definitions and declarations have the port attributes set.

This also resolves the issue with mismatched polarities with definitions/declarations and their interface attribute. This test fails before these changes

import magma as m
And2Decl = m.DeclareCircuit("And2", "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O", m.Out(m.Bit))
And2Defn = m.DefineCircuit("And2", "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O", m.Out(m.Bit))

assert And2Decl.interface.ports["I0"].isinput() == And2Defn.interface.ports["I0"].isinput()

with

    def test_declare_interface_polarity():
        And2Decl = m.DeclareCircuit("And2", "I0", m.In(m.Bit), "I1", m.In(m.Bit),
                                    "O", m.Out(m.Bit))
        And2Defn = m.DefineCircuit("And2", "I0", m.In(m.Bit), "I1", m.In(m.Bit),
                                   "O", m.Out(m.Bit))

>       assert And2Decl.interface.ports["I0"].isinput() == \
            And2Defn.interface.ports["I0"].isinput()
E       assert True == False
E        +  where True = <bound method Type.isinput of Bit>()
E        +    where <bound method Type.isinput of Bit> = Bit.isinput
E        +  and   False = <bound method Type.isinput of Bit>()
E        +    where <bound method Type.isinput of Bit> = And2.I0.isinput

[coveralls]

Pull Request Test Coverage Report for Build 1741

• 2 of 2 (100.0%) changed or added relevant lines in 1 file are covered.
• 2 unchanged lines in 2 files lost coverage.
• Overall coverage decreased (-0.02%) to 73.177%

---

Files with Coverage Reduction	New Missed Lines	%
magma/interface.py	1	87.59%
magma/backend/coreir_.py	1	88.76%

Totals
Change from base Build 1738:	-0.02%
Covered Lines:	4125
Relevant Lines:	5637

---

💛 - Coveralls

[coveralls]

Pull Request Test Coverage Report for Build 1741

• 2 of 2 (100.0%) changed or added relevant lines in 1 file are covered.
• 2 unchanged lines in 2 files lost coverage.
• Overall coverage decreased (-0.02%) to 73.177%

---

Files with Coverage Reduction	New Missed Lines	%
magma/interface.py	1	87.59%
magma/backend/coreir_.py	1	88.76%

Totals
Change from base Build 1738:	-0.02%
Covered Lines:	4125
Relevant Lines:	5637

---

💛 - Coveralls