Add ports

magma/circuit.py

@@ -77,6 +77,9 @@ def __new__(metacls, name, bases, dct):
         else:
             dct["debug_info"] = None
 
+        # Keep track of instances of this Circuit.
+        dct["my_instances"] = set()
+
 
         # create a new circuit class
         cls = type.__new__(metacls, name, bases, dct)
@@ -179,6 +182,18 @@ def find(cls, defn):
             defn[name] = cls
         return defn
 
+    def add_port(cls, name, typ):
+        if name in cls.IO.ports or name in cls.interface.ports:
+            raise ValueError(f"{name} already is a port of {cls.name}")
+        cls.IO.ports.update({name: typ})
+        cls.interface.add_port(name, typ, defn=cls, add_to_decl=True)
+        setattr(cls, name, cls.interface.ports[name])
+        for inst in cls.my_instances:
+            inst.IO.ports.update({name: typ})
+            inst.interface.add_port(name, typ, inst=inst, add_to_decl=False)
+            setattr(inst, name, inst.interface.ports[name])
+
+
 #
 # Abstract base class for circuits
 #
@@ -353,6 +368,10 @@ def __init__(self, *largs, **kwargs):
         if currentDefinition:
              currentDefinition.place(self)
 
+        defn = type(self)
+        assert self not in defn.my_instances
+        defn.my_instances.add(self)
+
     def __repr__(self):
         args = []
         for k, v in self.kwargs.items():

magma/interface.py

@@ -182,6 +182,17 @@ def __str__(self):
         return f'Interface({", ".join(f"{k}: {v}" for k, v in self.ports.items())})'
 
 
+def _make_port(name, typ, renamed_ports, inst, defn):
+    if   inst: ref = InstRef(inst, name)
+    elif defn: ref = DefnRef(defn, name)
+    else:      ref = AnonRef(name)
+    if name in renamed_ports:
+        ref.name = renamed_ports[name]
+    if defn:
+        typ = typ.flip()
+    return typ(name=ref)
+
+
 #
 # _DeclareInterface class
 #
@@ -202,20 +213,19 @@ def __init__(self, renamed_ports={}, inst=None, defn=None):
         args = OrderedDict()
 
         for name, port in zip(names, ports):
-            if   inst: ref = InstRef(inst, name)
-            elif defn: ref = DefnRef(defn, name)
-            else:      ref = AnonRef(name)
-
-            if name in renamed_ports:
-                ref.name = renamed_ports[name]
-
-            if defn:
-               port = port.flip()
-
-            args[name] = port(name=ref)
+            args[name] = _make_port(name, port, renamed_ports, inst, defn)
 
         self.ports = args
 
+    def add_port(self, name, typ, renamed_ports={}, inst=None, defn=None,
+                 add_to_decl=False):
+        assert name not in self.ports
+        port = _make_port(name, typ, renamed_ports, inst, defn)
+        self.ports.update({name: port})
+        if add_to_decl:
+            assert name not in self.Decl
+            type(self).Decl += (name, typ)
+
 class InterfaceKind(Kind):
     def __init__(cls, *args, **kwargs):
         super().__init__(*args, **kwargs)

tests/gold/test_add_ports.json

@@ -0,0 +1,18 @@
+{"top":"global.Foo",
+"namespaces":{
+  "global":{
+    "modules":{
+      "Foo":{
+        "type":["Record",[
+          ["I","BitIn"],
+          ["O","Bit"],
+          ["I2","BitIn"]
+        ]],
+        "connections":[
+          ["self.O","self.I"]
+        ]
+      }
+    }
+  }
+}
+}

tests/test_editing.py

@@ -0,0 +1,42 @@
+import magma as m
+from magma.testing import check_files_equal
+
+
+def test_add_ports_basic():
+    Foo = m.DefineCircuit("Foo", "I", m.In(m.Bit), "O", m.Out(m.Bit))
+    m.wire(Foo.I, Foo.O)
+    m.EndCircuit()
+
+    Foo.add_port("I2", m.In(m.Bit))
+    assert isinstance(Foo.I2, m._BitType)
+
+    # Instance Foo *after* adding a port.
+    foo = Foo()
+    assert isinstance(Foo.I2, m._BitType)
+
+    # Check compilation to CoreIR.
+    filename = "test_add_ports"
+    m.compile(f"build/{filename}", Foo, output="coreir")
+    check_files_equal(__file__, f"build/{filename}.json",
+                      f"gold/{filename}.json")
+
+
+def test_add_ports_previous_instance():
+    Foo = m.DefineCircuit("Foo", "I", m.In(m.Bit), "O", m.Out(m.Bit))
+    m.wire(Foo.I, Foo.O)
+    m.EndCircuit()
+
+    # Instacne Foo *before* adding a port.
+    foo = Foo()
+    assert not hasattr(foo, "I2")
+
+    Foo.add_port("I2", m.In(m.Bit))
+    assert isinstance(Foo.I2, m._BitType)
+
+    assert isinstance(Foo.I2, m._BitType)
+
+    # Check compilation to CoreIR.
+    filename = "test_add_ports"
+    m.compile(f"build/{filename}", Foo, output="coreir")
+    check_files_equal(__file__, f"build/{filename}.json",
+                      f"gold/{filename}.json")