This project aims to design a hardware implementation of UWB Receivers accordance with IEEE 802.15.4a standard. First, the whole UWB transceiver including channels and analog front-end is modeled in Simulink. Next, the digital receiver is implemented in Hardware Description Language. The system model is then used as verification environment to validate the behavior of the HDL receiver using Hardware-in-the-loop (HIL) emulator method. The HDL receiver works properly and use only small amount of hardware resource such that it can fit into small FPGA chip.